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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 10 • Date Oct. 2004

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Displaying Results 1 - 25 of 26
  • Table of contents

    Publication Year: 2004 , Page(s): c1 - c4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2004 , Page(s): c2
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  • Consistent noise models for analysis and design of CMOS circuits

    Publication Year: 2004 , Page(s): 1909 - 1915
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (424 KB) |  | HTML iconHTML  

    Simple, physics-based MOSFET noise models, valid over the linear, saturation, and subthreshold operation regions are presented. The consistency of the models representing series-parallel associations of transistors is verified. Simple formulas for hand analysis using the inversion level concept are developed. The proportionality between the flicker noise corner frequency and the transistor transit... View full abstract»

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  • A fully integrated dual-channel log-domain programmable preamplifier and filter for an implantable cardiac pacemaker

    Publication Year: 2004 , Page(s): 1916 - 1925
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (928 KB) |  | HTML iconHTML  

    A programmable-gain preamplifier and filter for detection of spontaneous heart activity in an implantable cardiac pacemaker is presented. The system is fully integrated in a standard 0.35-μm CMOS technology, including all auxiliary circuits. Two channels are available in order to process both atrial and ventricular signals. CMOS translinear circuits, with particular emphasis on log-domain techn... View full abstract»

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  • Investigation of phase noise of ring oscillators with time-varying current and noise sources by time-scaling thermal noise

    Publication Year: 2004 , Page(s): 1926 - 1939
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    This paper presents a new methodology of analyzing phase noise in a ring oscillator by time-scaling the thermal noise. Close-form solutions that relate the probability distribution and power-spectral density of the phase noise to circuit parameters have been obtained. These close-form solutions characterize the behavior of phase noise even when the circuit is varying with time in a nonlinear fashi... View full abstract»

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  • Process-insensitive low-power design of switched-capacitor integrators

    Publication Year: 2004 , Page(s): 1940 - 1952
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    A generalized analytical technique is developed to design power optimized switched-capacitor integrators taking process variations into account. It is shown that the performance of a robustly designed power optimum switched-capacitor integrator is a monotonic function of the slew rate and the transconductance of the amplifier. The framework provides an analytical solution for fabrication foundry i... View full abstract»

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  • Parasitic-aware RF circuit design and optimization

    Publication Year: 2004 , Page(s): 1953 - 1966
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1472 KB) |  | HTML iconHTML  

    RF circuit synthesis techniques based on particle swarm optimization and adaptive simulated annealing with tunneling are described, and comparisons of parasitic-aware designs of an RF distributed amplifier and a nonlinear power amplifier are presented. Synthesized in 0.35-μm digital CMOS using a single 3.3-V power supply, the designs provide an 8-dB gain and 8-GHz bandwidth for a four-stage dis... View full abstract»

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  • Positive feedback frequency compensation for low-voltage low-power three-stage amplifier

    Publication Year: 2004 , Page(s): 1967 - 1974
    Cited by:  Papers (17)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    The use of a new frequency compensation scheme for a three-stage operational amplifier is presented. The use of a positive feedback compensation (PFC) is employed to improve frequency response when compared to nested Miller compensation. A set of design equations is derived to give insight into the sizing of the amplifier. In addition, some characteristics relevant to the low-voltage low-power cir... View full abstract»

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  • A digital automatic tuning technique for high-order continuous-time filters

    Publication Year: 2004 , Page(s): 1975 - 1984
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (848 KB) |  | HTML iconHTML  

    A digital automatic tuning technique for high-order continuous-time filters is proposed. Direct tuning of overall response is achieved without separating individual biquad sections, eliminating switches and their parasitics. Output phase of each biquad section is tuned to known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and si... View full abstract»

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  • Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits

    Publication Year: 2004 , Page(s): 1985 - 1997
    Cited by:  Papers (47)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2824 KB) |  | HTML iconHTML  

    This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a nu... View full abstract»

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  • Design and analysis of power-CMOS-gate-based switched-capacitor boost DC-AC inverter

    Publication Year: 2004 , Page(s): 1998 - 2016
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1128 KB) |  | HTML iconHTML  

    A multistage power CMOS-transmission-gate-based (CMOS-TG) quasi-switched-capacitor (QSC) boost DC-AC inverter is proposed and integrated with a boost DC-DC converter for a step-up application with AC or DC load. In this paper, using CMOS-TG as a bidirectional switch, the various topologies can be integrated in the same configuration for achieving two functions: boosting and alternating; boosting f... View full abstract»

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  • Direct recursive structures for computing radix-r two-dimensional DCT/IDCT/DST/IDST

    Publication Year: 2004 , Page(s): 2017 - 2030
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (648 KB) |  | HTML iconHTML  

    In this paper, new recursive structures for computing radix-r two-dimensional (2-D) discrete cosine transform (DCT) and 2-D inverse DCT (IDCT) are proposed. The 2-D DCT/IDCT are first decomposed into cosine-cosine and sine-sine transforms. Based on indexes of transform bases, the regular pre-addition preprocess is established and the recursive structures for 2-D DCT/IDCT, which can be realized in ... View full abstract»

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  • A new split-radix FHT algorithm for length-q*2mDHTs

    Publication Year: 2004 , Page(s): 2031 - 2043
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (720 KB) |  | HTML iconHTML  

    In this paper, a new split-radix fast Hartley transform (FHT) algorithm is proposed for computing the discrete Hartley transform (DHT) of an arbitrary length N=q*2m, where q is an odd integer. The basic idea behind the proposed FHT algorithm is that a mixture of radix-2 and radix-8 index maps is used in the decomposition of the DHT. This idea and the use of an efficient indexing process... View full abstract»

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  • A neural network with O(N) neurons for ranking N numbers in O(1/N) time

    Publication Year: 2004 , Page(s): 2044 - 2051
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    In this paper, we propose a neural network for ranking a given set of N numbers in O(1/N) time. The ordering of a set of numbers based on their relative magnitudes, which is analogous to sorting, is a fundamental operation in many algorithms. In comparison with other sorting networks reported in the literature, the proposed network requires fewer neurons, and fewer interconnections between neurons... View full abstract»

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  • Decentralized nonlinear adaptive control for multimachine power systems via high-gain perturbation observer

    Publication Year: 2004 , Page(s): 2052 - 2059
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    This paper presents two novel decentralized nonlinear adaptive controllers (DNAC) for large-scale interconnected power systems, via state-feedback and output-feedback strategies respectively. In the both controllers, system perturbation, which includes all subsystem nonlinearities and interactions between subsystems, is estimated by a high-gain observer and then involved the decentralized adaptive... View full abstract»

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  • Perfect recovery and sensitivity analysis of time encoded bandlimited signals

    Publication Year: 2004 , Page(s): 2060 - 2073
    Cited by:  Papers (59)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    A time encoding machine is a real-time asynchronous mechanism for encoding amplitude information into a time sequence. We investigate the operating characteristics of a machine consisting of a feedback loop containing an adder, a linear filter, and a noninverting Schmitt trigger. We show that the amplitude information of a bandlimited signal can be perfectly recovered if the difference between any... View full abstract»

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  • Pinning a complex dynamical network to its equilibrium

    Publication Year: 2004 , Page(s): 2074 - 2087
    Cited by:  Papers (263)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1720 KB) |  | HTML iconHTML  

    It is now known that the complexity of network topology has a great impact on the stabilization of complex dynamical networks. In this work, we study the control of random networks and scale-free networks. Conditions are investigated for globally or locally stabilizing such networks. Our strategy is to apply local feedback control to a small fraction of network nodes. We propose the concept of vir... View full abstract»

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  • Minimization of quantization noise amplification in biorthogonal subband coders

    Publication Year: 2004 , Page(s): 2088 - 2097
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    Quantization noise amplification (QNA) restricts the coding gain (CG) in biorthogonal subband coders. Here, a coloring filter is introduced to color the quantization noise. The optimal coloring filter eliminating/minimizing QNA, with or without order restriction, is found for a given finite-impulse response filter bank (FB). An efficient implementation of the coloring filter is proposed. With the ... View full abstract»

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  • Determination of the impedance matching domain of impedance matching networks

    Publication Year: 2004 , Page(s): 2098 - 2106
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (808 KB) |  | HTML iconHTML  

    This paper investigates the impedance boundary of impedance matching networks analytically, graphically representing the resultant impedance matching domains. A set of explicit equations is derived to allow the rapid development of the impedance boundary of such networks. The equations are analyzed thoroughly, such that the impact each component has upon the resultant domain may be obtained. These... View full abstract»

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  • Corrections to “LMI-based Approach for Asymptotically Stability Analysis of Delayed Neural Networks”

    Publication Year: 2004 , Page(s): 2107
    Cited by:  Papers (2)
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  • 2005 IEEE International Symposium on Circuits and Systems (ISCAS 2005)

    Publication Year: 2004 , Page(s): 2108
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  • Special issue on biomedical circuits and systems: a new wave of technology

    Publication Year: 2004 , Page(s): 2109
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2004 , Page(s): 2110
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  • Quality without compromise [advertisement]

    Publication Year: 2004 , Page(s): 2111
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers Information for authors

    Publication Year: 2004 , Page(s): 2112
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras