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Nanotechnology, IEEE Transactions on

Issue 4 • Date Dec. 2003

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Displaying Results 1 - 25 of 34
  • Modeling of the programming window distribution in multinanocrystals memories

    Publication Year: 2003 , Page(s): 277 - 284
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB) |  | HTML iconHTML  

    In this paper, the impact of the Si nanocrystals technological fluctuations on the programming window dispersion of multi nanocrystals memory is thoroughly investigated. Technological dispersions of different nanocrystals populations, directly measured by high-resolution transmission electron microscopy, are used as starting points for the modeling of the device characteristics. Numerical Monte Carlo simulations as well as an original compact modeling, based on the compound distributions (CD) statistics, are here presented. Exact analytical results (CD model), approximated analytical results (CD+Central Limit Theorem model) and numerical results (numerical convolution) are deeply discussed. Finally, the good agreement between our simulations and experimental data of ultrascaled nanocrystal devices, made by conventional UV lithography or by e-beam lithography, definitively confirms the validity of our theoretical approach. View full abstract»

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  • Twin-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory by inverted sidewall patterning (TSM-ISP)

    Publication Year: 2003 , Page(s): 246 - 252
    Cited by:  Papers (8)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (914 KB)  

    We have proposed a new twin-bit silicon-oxide-nitride-oxide-silicon memory (TSM)-inverted sidewall patterning (ISP) cell which has twin oxide-nitride-oxides (ONOs) physically separated by the ISP method under one control gate. This TSM-ISP can control the trapped charge distribution and make diffusion barrier of charges, so that program/erase (P/E) endurance and retention can be increased. The trapping nitride is narrow enough to reduce hot-hole erase times. To estimate the new device characteristics, we have devised a special simulation method of silicon-oxide-nitride-oxide-silicon (SONOS) by implementing a simple idea in the conventional device simulator, "MEDICI." By placing the floating nodes in nitride with adjusted density, which is supposed to play the role of charge traps in nitride, we can estimate not only the conventional SONOS characteristics, but also the new SONOS characteristics, such as TSM-ISP. View full abstract»

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  • Erbium silicided n-type Schottky barrier tunnel transistors for nanometer regime applications

    Publication Year: 2003 , Page(s): 205 - 209
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (243 KB) |  | HTML iconHTML  

    The theoretical and experimental current-voltage characteristics of Erbium silicided n-type Schottky barrier tunneling transistors (SBTTs) are discussed. The theoretical drain current to drain voltage characteristics show good correspondence with the experimental results in 10-μm-long channel n-type SBTTs. From these results, the extracted Schottky barrier height is 0.24 eV. The experimentally manufactured n-type SBTTs with 60-nm gate lengths show typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 105 at low-drain voltage regime in drain current to gate voltage characteristics. However, the on/off ratio tends to decrease as the drain voltage increases. From the numerical simulation results, the increase of off-current is mainly attributed to the thermionic current and the increase of drain current is mainly attributed to the tunneling current. View full abstract»

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  • On the FinFET extension implant energy

    Publication Year: 2003 , Page(s): 285 - 290
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (383 KB) |  | HTML iconHTML  

    The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the Ioff-Ion performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current. View full abstract»

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  • Monte Carlo simulation of symmetric and asymmetric double-gate MOSFETs using Bohm-based quantum correction

    Publication Year: 2003 , Page(s): 291 - 294
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (349 KB) |  | HTML iconHTML  

    In light of increasing interest in the development of double gate (DG) CMOS technology that extends the device scaling limit, the relative merit of symmetric versus asymmetry DG-MOSFETs is studied using the quantum corrected Monte Carlo (MC) method. A recently developed Bohm-based quantum correction model is applied to the MC simulation of DG-MOSFETs. The drain current is first studied as the thickness of the silicon layer is scaled. Then results of the charge density and potential for asymmetric and symmetric devices under the same bias conditions are compared. Also analyzed is how the drain induced barrier lowering is affected by the channel length. View full abstract»

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  • Regularly coiled carbon nanotubes

    Publication Year: 2003 , Page(s): 362 - 367
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (611 KB) |  | HTML iconHTML  

    Regularly coiled carbon nanotubes, their structure, and formation mechanism are puzzling questions. The first models were based on the very regular incorporation of a small fraction (of the order of 10%) of nonhexagonal (n-Hx) rings: (pentagons and heptagons) in a perfect hexagonal (Hx) lattice. It is difficult to understand by which mechanism takes place such a regular incorporation of isolated n-Hx rings. In this paper, a new family of Haeckelite nanotubes is generated in a systematic way by rolling up a two-dimensional three-fold coordinated carbon network composed of pentagon-heptagon pairs and hexagons in proportion 2 : 3. In this model, the n-Hx rings are treated like regular building blocks of the structure. Cohesion energy calculation shows that the stability of the generated three-dimensional Haeckelite structures falls between that of straight carbon nanotubes and that of C60. Electronic density of states of the Haeckelite computed with a tight-binding Hamiltonian that includes the C-π orbitals only shows that the structures are semiconductor. The relation of the structures with experimental observations is discussed. View full abstract»

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  • Vibrational properties of boron-nitride nanotubes: effects of finite length and bundling

    Publication Year: 2003 , Page(s): 341 - 348
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (626 KB) |  | HTML iconHTML  

    We present ab initio calculations of phonons in single-wall boron-nitride (BN) nanotubes. Raman and infrared (IR) active modes of isolated and infinitely long tubes are evaluated according to the nonsymmorphic rod groups of BN nanotubes. For tubes of finite length, the selection rules are less restrictive and give rise to additional modes, which may be observed in Raman and IR spectroscopy with an intensity depending on the tube length. Bundling of tubes is shown to have little effect on the phonon frequencies. However, arranging tubes in a large periodic array (larger than the wavelength of incoming light) gives rise to a strong frequency shift (longitudinal-optical-transverse-optical splitting) of certain modes due to the establishing of a macroscopic electric field. Modes of A1 symmetry experience a shift for laser light along the tube axis and E1 modes are split for light incidence in the perpendicular direction. View full abstract»

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  • Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

    Publication Year: 2003 , Page(s): 210 - 216
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (558 KB) |  | HTML iconHTML  

    We proposed "reverse-order source/drain formation with double offset spacer" (RODOS) structure for low-power and high-speed applications. Both simulation and experimental data were used to evaluate the potential of the structure. It showed improved performance in terms of poly-depletion effect, dc characteristics, gate delay (CV/I), switching energy (CV2) and linearity (VIP3). It satisfied all the requirements of LOP and LSTP for 90 nm technology node in ITRS 2002. Simulation predicted 794 μA/μm in on-current, 0.1 nA/μm in off-current, 65 mV/V in DIBL, 80 mV/dec in SS, 1.29 ps in gate delay, 198 GHz in fT and 0.151 fJ in switching energy in addition to enhanced linearity. Finally, we confirmed the high feasibility and potential of the RODOS MOSFET's for low-power and high-speed applications such as an LNA in portable communication appliances. View full abstract»

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  • Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process

    Publication Year: 2003 , Page(s): 198 - 204
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (698 KB) |  | HTML iconHTML  

    The electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs (FXMOSFETs) fabricated by a wet process have experimentally and systematically been investigated. The almost ideal S-slope of 64 mV/decade was obtained for the fabricated 20 nm Si-Fin and 125 nm gate-length FXMOSFET. This excellent subthreshold characteristic shows that the quality of the rectangular Si-Fin channel with (111)-oriented sidewall is good enough to realize high-performance FXMOSFETs. The current and transconductance multiplication accurately proportional to a number of 30 nm Si-Fin channels was confirmed in the fabricated multi-fin FXMOSFETs. The systematic investigation of the electrical characteristics of the fabricated FXMOSFETs in the 20-110-nm Si-Fin and 2.3-5.2-nm gate oxide regimes reveals that short-channel effects can be effectively suppressed by reducing the Si-Fin thickness to 20 nm or less. The developed processes are quite attractive for fabrication of ultranarrow Si-Fin channel double-gate MOSFETs. View full abstract»

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  • A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics

    Publication Year: 2003 , Page(s): 253 - 257
    Cited by:  Papers (8)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (943 KB) |  | HTML iconHTML  

    We have demonstrated a novel three-dimensional multibridge-channel metal-oxide-semiconductor field-effect transistor (MBCFET). This transistor was successfully fabricated using a conventional complementary metal-oxide-semiconductor process. We introduce the fabrication technologies and electrical characteristics of MBCFET in comparison with a conventional planar MOSFET. The MBCFET has more benefits than a conventional MOSFET. It shows 4.6 times larger current drivability than a planar MOSFET. This is due to the vertically stacked multibridge channels. The subthreshold swing of MBCFET is 61 mV/dec, which is almost an ideal value due to the thin body surrounded by gate. Based on a simulation result, we show that the MBCFET will have a large on-off state current ratio at short channel transistors. View full abstract»

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  • Switching of single-electron oscillations in dual-gated nanocrystalline silicon point-contact transistors

    Publication Year: 2003 , Page(s): 271 - 276
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (761 KB) |  | HTML iconHTML  

    Switching of single-electron transport is observed in point-contact transistors fabricated in nanocrystalline silicon thin films, where the grain size is ∼10 to 40 nm. The effects may be associated with electrostatic coupling between the grains. At 4.2 K, single-electron oscillations in the device current are switched as a function of the voltages on two separate gates. This is investigated further using single-electron Monte Carlo simulation of a model with two charging grains in parallel and intergrain capacitive coupling. A change in the electron number of a grain occurs due to charging of the other grain by a single electron, causing bistable regions in charge stability versus gate voltage. These effects depend not only on the coupling capacitance but also on the cross capacitances between the grains and the two gates. View full abstract»

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  • Hybrid silicon nanocrystal silicon nitride dynamic random access memory

    Publication Year: 2003 , Page(s): 335 - 340
    Cited by:  Papers (18)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1025 KB)  

    This paper introduces a silicon nanocrystal-silicon nitride hybrid single transistor cell for potential dynamic RAM (DRAM) applications that stores charge in silicon nanocrystals or a silicon nitride charge trapping layer or both. The memory operates in the direct tunneling regime for the tunnel oxide and so presents the possibility of a DRAM with good cycling endurance. The silicon nanocrystals of this hybrid device present intermediate states that facilitate tunneling transport to and from the nitride layer. Short time measurements show that the hybrid silicon nanocrystal silicon nitride based DRAM cell programs and erases much faster than a plain SONOS implementation while offering better data retention, memory signal and longer refresh time than a silicon nanocrystal type DRAM. View full abstract»

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  • 50-nm fully depleted SOI CMOS technology with HfO2 gate dielectric and TiN gate

    Publication Year: 2003 , Page(s): 324 - 328
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO2 gate dielectric at the 50-nm physical gate length. Symmetric VT is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a Ion=500 μA/μm and Ioff=10 nA/μm at VDD=1.2 V for nMOSFET and Ion=212 μA/μm and Ioff=44 pA/μm at VDD=-1.2 V for pMOSFET, with a CET=30 Å and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at VDD=1.2 V are also realized. View full abstract»

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  • A new model for including discrete dopant ions into Monte Carlo simulations

    Publication Year: 2003 , Page(s): 193 - 197
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (882 KB) |  | HTML iconHTML  

    A new method for including discrete dopants into Monte Carlo device simulation is presented. The method uses a molecular dynamics treatment of the electron-electron and electron-ion interaction that includes quantum mechanical effects via an effective potential. Modeling the positive ions with an effective potential results in an energy minimum of 50.7 meV at the positive ion, which correlates well to common donor energy levels in silicon. We find that the method produces the expected mobility reduction in the ID-VG characteristics of thin SOI MOSFETs. View full abstract»

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  • Experimental observation and quantum modeling of electron irradiation on single-wall carbon nanotubes

    Publication Year: 2003 , Page(s): 349 - 354
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB) |  | HTML iconHTML  

    In situ experiments, based on electron irradiation at high temperature in a transmission electron microscope, are used to investigate isolated, packed and crossing single-wall nanotubes. During continuous, uniform atom removal, surfaces of isolated single-wall nanotubes heavily reconstruct leading to drastic dimensional changes. In bundles, coalescence of single-wall nanotubes is observed and induced by vacancies via a zipper-like mechanism. "X", "Y", and "T" carbon nanostructures are also fabricated by covalently connecting crossed single-wall nanotubes in order to pave the way toward controlled fabrication of nanotube based molecular junctions and network architectures exhibiting exciting electronic and mechanical behavior. Each experiment is followed by quantum modeling in order to investigate the effect of the irradiation process at the atomic level. View full abstract»

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  • CMOS/nano co-design for crossbar-based molecular electronic systems

    Publication Year: 2003 , Page(s): 217 - 230
    Cited by:  Papers (73)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1356 KB) |  | HTML iconHTML  

    Future electronic systems will need to adopt novel nanoelectronic solutions to keep pace with Moore's Law. Crossbar-based molecular electronics are among the most promising of nanotechnologies. However, circuits similar to the conventional mainstream electronics of today will have a presence in future complex systems for some time. This paper presents a circuit paradigm where silicon and molecular electronics are integrated. We discuss methods for realizing memory and logic using nanoscale crossbars as well as for interfacing the crossbars to CMOS circuitry. Using custom nanoscale device models, we perform circuit simulation and analysis of the crossbar circuits and the peripheral CMOS circuitry. Finally, we present a design methodology to accompany the CMOS/nano paradigm. View full abstract»

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  • Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices

    Publication Year: 2003 , Page(s): 258 - 264
    Cited by:  Papers (16)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (751 KB) |  | HTML iconHTML  

    In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain. View full abstract»

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  • Coulomb-blockade in nanometric Si-film silicon-on-nothing (SON) MOSFETs

    Publication Year: 2003 , Page(s): 295 - 300
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1035 KB) |  | HTML iconHTML  

    The advantages of using architectures with gate nonoverlapped with source/drain have already been demonstrated in order to measure controlled single electron effects in planar MOSFETs. In this paper, we performed nonoverlapped silicon-on-nothing (SON) transistors with Si-film from 15 down to 9 nm. This leads to the fabrication of a quantum box (QB) defined by two lateral potential barriers in a thin Si-film (due to the camel's back shape of the potential along the channel), and by two vertical potential barriers due to the gate oxide and to the buried dielectric of the SON architecture. This small volume device behaves like a quantum box, and we demonstrated that its own capacitance and consequently the Coulomb-blockade properties were mainly determined by the conduction film thickness. As the SON technology allows us to perform higly-performant fully depleted devices from bulk substrate, we will see in this paper that such devices can easily be adapted in order to fabricate three-dimensional QB, which becomes an alternative to fabricate SET with standard CMOS process. View full abstract»

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  • Large Coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFETs formed by slight oxidation process

    Publication Year: 2003 , Page(s): 241 - 245
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (394 KB)  

    We propose a new fabrication technique of room-temperature operating silicon single-electron transistors (SETs). The devices are in the form of ultranarrow wire channel MOSFETs, where a sub-10-nm channel is formed by wet etching and slight thermal oxidation. Large Coulomb blockade (CB) oscillations whose peak-to-valley current ratio at room temperature is as high as 6.8 are observed in the fabricated ultranarrow wire channel MOSFETs. It is found that larger CB oscillations are obtained in the ultranarrow wire channel SETs than in the point-contact channel SETs. It is considered that the potential fluctuations induced during the channel formation processes give rise to multiple-dot SET structures in the ultranarrow wire channel MOSFETs. View full abstract»

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  • Electrostatics of nanowire transistors

    Publication Year: 2003 , Page(s): 329 - 334
    Cited by:  Papers (38)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1042 KB) |  | HTML iconHTML  

    The electrostatics of nanowire transistors are studied by solving the Poisson equation self-consistently with the equilibrium carrier statistics of the nanowire. For a one-dimensional, intrinsic nanowire channel, charge transfer from the metal contacts is important. We examine how the charge transfer depends on the insulator and the metal/semiconductor Schottky barrier height. We also show that charge density on the nanowire is a sensitive function of the contact geometry. For a nanowire transistor with large gate underlaps, charge transferred from bulk electrodes can effectively "dope" the intrinsic, ungated region and allow the transistor to operate. Reducing the gate oxide thickness and the source/drain contact size decreases the length by which the source/drain electric field penetrates into the channel, thereby, improving the transistor characteristics. View full abstract»

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  • Enhancement of adjustable threshold voltage range by substrate bias due to quantum confinement in ultrathin body SOI pMOSFETs

    Publication Year: 2003 , Page(s): 314 - 318
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (503 KB) |  | HTML iconHTML  

    The body effect in ultrathin body (silicon-on-insulator) SOI MOSFETs has been investigated by experiments and modeling. It is demonstrated for the first time that the adjustable threshold voltage range by substrate bias is enhanced due to the quantum confinement effect in ultrathin body SOI. The enhancement ratio of the adjustable threshold voltage range in a 4.3-nm-thick SOI MOSFET compared to 11.7-nm-thick one is around 10%. This indicates that ultrathin body MOSFETs are useful not only for suppressing the short channel effects, but also for suppressing the off-leak current in the variable threshold CMOS scheme. View full abstract»

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  • New insights in high-energy electron emission and underlying transport physics of nanocrystalline Si

    Publication Year: 2003 , Page(s): 301 - 307
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (398 KB) |  | HTML iconHTML  

    This paper presents quantitative analysis of electron emission from nanocrystalline Si dots, and discusses its mechanism based on the calculations of electronic and phononic states. Analysis of emission energy distribution measured from the vacuum level shows that the energy at the peak of the distribution increases linearly with increasing voltage applied across the nanocrystalline Si system. The slope of the linear law is unity, regardless of process conditions. Increasing voltage significantly changes the shape of the distribution at the energies smaller than the peak, while it has minimal impact at the energies larger than the peak. Both the conventional field emission model and the metal-oxide-semiconductor model fail to explain those behaviors. Calculations of electronic and phononic states in a chain of the nanocrystalline Si dots indicate a possibility of strong suppression of electron energy relaxation, which may be a possible mechanism of the high-energy electron emission phenomena. View full abstract»

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  • Fabrication of resonant-tunneling diodes by Sb surfactant modified growth of Si films on CaF2/Si

    Publication Year: 2003 , Page(s): 236 - 240
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (469 KB)  

    Molecular beam epitaxy growth of Si thin films on CaF2/Si(111) substrates has been studied. A surfactant-modified solid-phase epitaxy method, where the room temperature Si deposition was followed by annealing under Sb flux, resulted in a continuous, smooth epitaxial crystalline Si film with a sharp (√3×√3)R30° reconstruction and a surface roughness of 0.15-nm rms for a 2.8-nm Si thin film. This growth technique was used to fabricate CaF2/Si/CaF2 double-barrier resonant tunneling diodes in SiO2 windows patterned on Si(111) substrates. A negative differential resistance (NDR) peak was found at ∼0.35 V at 77 K, and the current density at the NDR peak was estimated to be 3-4 orders of magnitude higher than in earlier reports. View full abstract»

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  • Building and testing organized architectures of carbon nanotubes

    Publication Year: 2003 , Page(s): 355 - 361
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (790 KB) |  | HTML iconHTML  

    This paper will focus on the directed assembly of multiwalled carbon nanotubes on various substrates into highly organized structures that include vertically and horizontally oriented arrays, ordered fibers and porous membranes. The concept of growing such architectures is based on growth selectivity on certain surfaces compared to others. Selective placement of ordered nanotube arrays is achieved on patterned templates prepared by lithography or oxide templates with well-defined pores. The growth of nanotubes is achieved by chemical vapor deposition using hydrocarbon precursors and vapor phase catalyst delivery. The new technique developed in our laboratory allows enormous flexibility in building a large number of complex structures based on nanotube building units. This paper will provide an insight into the creation process of the longest (single walled) nanotube strands. We will also discuss some of our recent efforts in creating nanotube circuits selectively and controllably and on the spatially resolved electronic properties of nanotubes. View full abstract»

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  • Ambipolar Coulomb blockade characteristics in a two-dimensional Si multidot device

    Publication Year: 2003 , Page(s): 231 - 235
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (621 KB)  

    A two-dimensional Si multidot channel field-effect transistor is fabricated from a silicon-on-insulator material and the electrical characteristics are studied. The multidots are formed using a nanometer-scale local oxidation of Si process developed in our laboratory. The device shows ambipolar characteristics because of Schottky source and drain, i.e., the carriers are electrons for positive gate voltage and holes for the negative one. It is shown that Coulomb blockade (CB) oscillations are clearly observed for both of the electrons and holes at measurement temperatures up to 60 K. Both CB characteristics show nonperiodic oscillation and an open Coulomb diamond. These features are ascribed to the single electron/hole tunneling in the Si multidot channel. View full abstract»

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Aims & Scope

The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.

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Meet Our Editors

Editor-in-Chief
Fabrizio Lombardi
Dept. of ECE
Northeastern Univ.