By Topic

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 12 • Date Dec. 2003

Filter Results

Displaying Results 1 - 18 of 18
  • Editorial

    Publication Year: 2003 , Page(s): 905
    Save to Project icon | Request Permissions | PDF file iconPDF (138 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Author index

    Publication Year: 2003 , Page(s): 1028 - 1032
    Save to Project icon | Request Permissions | PDF file iconPDF (191 KB)  
    Freely Available from IEEE
  • Subject index

    Publication Year: 2003 , Page(s): 1032 - 1045
    Save to Project icon | Request Permissions | PDF file iconPDF (261 KB)  
    Freely Available from IEEE
  • Gain-enhanced feedforward path compensation technique for pole-zero cancellation at heavy capacitive loads

    Publication Year: 2003 , Page(s): 933 - 941
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (562 KB) |  | HTML iconHTML  

    An improved frequency compensation technique is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor to form a composite gain-enhanced feedforward stage in a two-stage amplifier so as to broaden the gain bandwidth via low-frequency pole-zero cancellation at heavy capacitive loads, but yet without increasing substantial power consumption. The technique has been confirmed by the experimental results. An operational amplifier has been designed to drive a capacitive load of 300 pF. The amplifier exhibits a dc gain of 87 dB, a gain bandwidth of 10.4 MHz at 63.7° phase margin, an average slew rate of 3.5 V/μs, a compensation capacitor of only 6 pF while consuming 2.45 mW at a 3-V supply in a standard 0.6-μm CMOS technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A DDS-based PLL for 2.4-GHz frequency synthesis

    Publication Year: 2003 , Page(s): 1007 - 1010
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    In this transactions brief, we present a direct digital synthesizer (DDS)-based phase-locked loop (PLL), for frequency synthesis at 2.4 GHz with 80-MHz tuning range. The DDS signal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. These characteristics are often incompatible both in integer and fractional dividers PLL. A prototype was fabricated on PCBs and tested. The settling time is about 3 μs for 0.1 ppm (240 Hz) accuracy. Worst-case spurs are -53 dBc at 8-MHz offset from the carrier. The integrated phase noise in the band 1 kHz -1 MHz is 0.9° rms. This architecture is also suitable for direct frequency modulation, without necessitating any calibration system. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Adaptive filter design subject to output envelope constraints and bounded input noise

    Publication Year: 2003 , Page(s): 1023 - 1026
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB) |  | HTML iconHTML  

    This transactions brief is concerned with designing adaptive filters subject to output envelope constraints in the presence of bounded noise at the input channel. The bound on the noise is used to form the input mask that contains all possible input signals corrupted by noise. The optimal envelope-constrained filter is designed with respect to the entire input mask. A cubic smoothing function is applied to implement the constraint approximation, which paves the way for establishing adaptive algorithms. The adaptive envelope-constrained filter thus designed, achieves guaranteed satisfaction of the output envelope constraints as long as it has converged. Computer simulations that support the theoretical findings are given. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An experimental evaluation of error spectrum shaping applied to mixed-signal image convolutions

    Publication Year: 2003 , Page(s): 950 - 962
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1194 KB) |  | HTML iconHTML  

    In this experimental research paper, analog circuits are manufactured and their performance evaluated for suitability in performing FIR image filtering with the convolution kernel and data altered via error spectrum shaping and oversampling so as to preclude corruption by circuit imperfections. Similar to the one-dimensional (1-D) binary signals output by Sigma Delta analog-to-digital converters, the representational noise caused by the circuit's resolution inaccuracy is pushed into an unused portion of the spectrum in these analog signals, permitting the inband portion of the oversampled signal to be more effectively represented and processed by imperfect circuits. An analysis of image convolutions performed using the circuits' data establishes that ESS is successful at reducing the computational error in certain analog image convolutions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • RF bandpass filter design based on CMOS active inductors

    Publication Year: 2003 , Page(s): 942 - 949
    Cited by:  Papers (60)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1392 KB) |  | HTML iconHTML  

    In this paper, a second-order RF bandpass filter based on active inductor has been implemented in a 0.35 μm CMOS process. Issues related to the intrinsic quality factor and dynamic range of the CMOS active inductor are addressed. Tuned at 900 MHz with Q=40, the filter has 28-dB spurious-free-dynamic-range (SFDR) and total current consumption (including buffer stage) is 17 mA with 2.7-V power supply. Experimental results also show the possibility of using them to build higher order RF filter and voltage-controlled oscillator (VCO). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Roundoff noise analysis in digital systems for arbitrary sampling rate conversion

    Publication Year: 2003 , Page(s): 1016 - 1023
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    In this brief, the impact of finite-signal wordlengths on the performance of digital systems for arbitrary sampling rate conversion (ASRC), where input and output sampling rates are derived from independent clock generators, is investigated. For two different efficient realizations of ASRC the noise power due to both, input/output quantization and multiplication roundoff errors, is determined as a function of the signal wordlengths and system parameters, respectively. The obtained system degradation, estimated on basis of the standard model of quantization by rounding, is verified by simulation. As a result, simple design rules for the appropriate selection of the various ASRC-inherent signal wordlengths are given subject to the required system performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low error fixed-width CSD multiplier with efficient sign extension

    Publication Year: 2003 , Page(s): 984 - 993
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (639 KB)  

    This paper presents an error compensation method for fixed-width canonic signed digit (CSD) multipliers that receive a W-bit input and produce a W-bit product. To efficiently compensate for the quantization error, the truncated bits are divided into two groups (major group and minor group) depending upon their effects on the quantization error. The desired error compensation bias is first expressed in terms of the truncated bits in the major group. Then the effects of the other truncated bits in the minor group are taken care of by a probabilistic estimation. Also, an efficient sign extension reduction method applied to the fixed-width CSD multipliers is proposed. By simulations, it is shown that 25% reduction in the truncation error and 13% hardware complexity can be achieved by the proposed error compensation and sign extension reduction methods, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new low voltage precision CMOS current reference with no external components

    Publication Year: 2003 , Page(s): 928 - 932
    Cited by:  Papers (15)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 μm mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1% over a temperature range of -20°C to +100°C and a supply voltage range of 1.4 V to 3 V with ±30% tolerance for all of the used on- chip resistors. The maximum current variation is slightly less than the oxide thickness variation in the process corners. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • M-channel lifting factorization of perfect reconstruction filter banks and reversible M-band wavelet transforms

    Publication Year: 2003 , Page(s): 963 - 976
    Cited by:  Papers (30)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (795 KB) |  | HTML iconHTML  

    An intrinsic M-channel lifting factorization of perfect reconstruction filter banks (PRFBs) is presented as an extension of Sweldens' conventional two-channel lifting scheme. Given a polyphase matrix E(z) of a finite-impulse response (FIR) M- channel PRFB with det(E(z))=z-K, K∈Z, a systematic M-channel lifting factorization is derived based on the Monic Euclidean algorithm. The M-channel lifting structure provides an efficient factorization and implementation; examples include optimizing the factorization for the number of lifting steps, delay elements, and dyadic coefficients. Specialization to paraunitary building blocks enables the design of paraunitary filter banks based on lifting. We show how to achieve reversible, possibly multiplierless, implementations under finite precision, through the unit diagonal scaling property of the Monic Euclidean algorithm. Furthermore, filter-bank regularity of a desired order can be imposed on the lifting structure, and PRFBs with a prescribed admissible scaling filter are conveniently parameterized. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Gradient error cancellation and quadratic error reduction in unary and binary D/A converters

    Publication Year: 2003 , Page(s): 1002 - 1007
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (743 KB) |  | HTML iconHTML  

    A novel geometrical arrangement of unit cells in a digital-analog converter (D/A) converter, along with a new switching sequence results in full cancellation of gradient errors. This is achieved without using quad, quad-quad, or triple-quad techniques which increase the number of units by a factor of 4 or 16. In an M-b D/A, by proper arrangement of (2M-1) units in a matrix having odd number of rows and odd number of columns, a central unit is established allowing complete cancellation of gradient errors. The decoding logic has the same simplicity of a standard row-column decoder with the advantage of being half in size. This technique, called "symmetric-pair switching," avoids large routing between multiple subunits in quad, quad-quad and triple-quad techniques thus improving D/A performance. Another independent technique, "balanced-ring switching," is introduced for reduction of quadratic errors. This technique achieves an order of magnitude reduction in quadratic errors compared to the "Q2 Random Walk" technique. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Digital quadrature demodulator with four phases mixing for digital radio receivers

    Publication Year: 2003 , Page(s): 1011 - 1015
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (287 KB) |  | HTML iconHTML  

    A digital quadrature demodulator is proposed that gives the complex components of the received signal. The adoption of a modulated local oscillator (LO) with four periodic phase states synchronized with the sampling avoids the use of two mixing paths, simplifying the radio-frequency (RF) circuits and allowing an effective VLSI integration. This receiver minimizes the in-phase/quadrature (I/Q) mismatch and, with an adequate choice of the periodic modulating sequence, avoids the direct current (dc) offset of the direct conversion receivers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of switched-capacitor common-mode feedback circuit

    Publication Year: 2003 , Page(s): 906 - 917
    Cited by:  Papers (53)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB) |  | HTML iconHTML  

    A detailed analysis of the dc behavior of switched-capacitor common-mode feedback circuit (SC-CMFB) is presented. A mathematical model, useful for analysis, is developed and the expressions for the output common-mode (CM) voltage, with and without considering the charge injection of switches and leakage currents, are derived. Further, the expression for dc CM settling time, is presented. The effect of parasitic capacitances, dc CM gain, charge injection error, and leakage currents, on the steady-state value of the dc CM voltage is analyzed and design guidelines to minimize these errors are presented. Finally, an improved version of the SC-CMFB circuit is analyzed. This circuit has very low errors due to charge injection and leakage currents and settles much faster than the traditional SC-CMFB circuit. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evolutionary synthesis of digital filter structures using genetic programming

    Publication Year: 2003 , Page(s): 977 - 983
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (403 KB) |  | HTML iconHTML  

    This paper presents a synthesis method for infinite-impulse response (IIR) digital filter structures using genetic programming with automatically defined functions (GP-ADF). In the proposed method, digital filter structures are represented as S-expressions with subroutines, which are written directly from the set of difference equations. This paper also shows the condition for the constructing the S-expressions that represent the filter structures without delay-free loops. Numerical examples synthesize two-filter structures: the low-coefficient sensitivity fourth-order filter structure and the low-output roundoff noise second-order filter structure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of third-order intermodulation distortion in common-emitter BJT and HBT amplifiers

    Publication Year: 2003 , Page(s): 994 - 1001
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (479 KB) |  | HTML iconHTML  

    This transactions brief presents an electro-thermal Volterra model for calculating third-order intermodulation distortion (IM3) in common emitter (CE) bipolar junction transistor (BJT) RF amplifiers. The model includes nonlinearities caused by input-output cross products, which previous studies have tended to overlook, in spite of their significance for RF devices. The nonlinear I-V and Q-V sources of the model are presented also as functions of temperature to analyze how distortion is affected by dynamic temperature variations inside the device. The model is organized to facilitate the recognition of different IM3 components, especially those arising from out-of-band second-order distortion voltages. In addition, this transactions brief presents a technique for characterizing the nonlinearity coefficients of a RF power BJT and studies the behavior of intermodulation distortion as a function of bias point and of out-of-band impedance matching. Optimum bias and matching points are established for the test amplifier, and a good correlation is demonstrated between the calculated and measured data. Finally, this transactions brief shows that some serious memory effects cannot be seen when simulated using the traditional Spice BJT model, but can be detected using the polynomial Volterra model. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 1.5-V MOS translinear loops with improved dynamic range and their applications to current-mode signal processing

    Publication Year: 2003 , Page(s): 918 - 927
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (519 KB) |  | HTML iconHTML  

    Novel MOS translinear loop topologies for very low-voltage applications are presented. The inclusion of dc level shifting, together with a novel biasing scheme based on two MOS transistors in the triode region, allows the operation of the loops at supply voltages as low as VGS+2VDSsat maintaining at the same time a large dynamic range. Several current-mode translinear circuits, both static and dynamic, i.e., geometric mean, squarer/divider, multiplier and square-root-domain filters, are implemented following this approach, demonstrating on silicon the proposed techniques. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope