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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 12 • Date Dec. 2002

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Displaying Results 1 - 7 of 7
  • Comments on "Current-mode biquad with a minimum number of passive elements" [with reply]

    Publication Year: 2002 , Page(s): 783 - 784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (150 KB) |  | HTML iconHTML  

    For original article by O. Cicekoglu see ibid., vol.48, p.221-2 ( Feb. 2001). View full abstract»

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  • Author's reply

    Publication Year: 2002 , Page(s): 783 - 784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB) |  | HTML iconHTML  

    First Page of the Article
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  • Necessary and sufficient conditions for mismatch shaping in a general class of multibit DACs

    Publication Year: 2002 , Page(s): 748 - 759
    Cited by:  Papers (15)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1528 KB) |  | HTML iconHTML  

    Multibit digital-to-analog converters (DACs) are often constructed by combining several 1-bit DACs of equal or different weights in parallel. In such DACs, component mismatches give rise to signal dependent error that can be viewed as additive DAC noise. In some cases these DACs use dynamic element matching techniques to decorrelate the DAC mismatch noise from the input sequence and suppress its power in certain frequency bands. Such DACs are referred to as mismatch-shaping DACs and have been used widely as enabling components in state-of-the-art ΔΣ data converters. Several different mismatch-shaping DAC topologies have been presented, but theoretical analyses have been scarce and no general unifying theory has been presented in the previously published literature. This paper presents such a unifying theory in the form of necessary and sufficient conditions for a multibit DAC to be a mismatch-shaping DAC and applies the conditions to evaluate the DAC noise generated by several of the previously published mismatch-shaping DACs and qualitatively compare their behavior. View full abstract»

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  • On-line extraction of soft decoding information and applications in VLSI turbo decoding

    Publication Year: 2002 , Page(s): 760 - 769
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB) |  | HTML iconHTML  

    In this paper, a set of variables which can be easily computed in the course of iterative decoding of turbo decoders named turbo decoding metrics (TDMs) are introduced. TDMs are measured twice per iteration. According to the measured values, a lot of information other than the signal-to-noise ratio (SNR) in the received data, such as how good (or bad) the current decoding block is and how close to the convergence the current decoding is, can be obtained. Detailed discussions are provided regarding why these variables are considered. Based on the measured TDMs after the first iteration, an approximate channel reliability value (denoted as Lc) can be obtained for MAP-based turbo decoders. Simulation results show that there is no performance degradation if approximated Lc values are used instead of using exact values. It is also shown that the adaptive decoding approach employing TDMs is more efficient than all existing methods in terms of hardware and latency. Other applications of TDMs are also pointed out. View full abstract»

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  • A double-sampling SC-resonator for low voltage bandpass ΔΣ-modulators

    Publication Year: 2002 , Page(s): 737 - 747
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB) |  | HTML iconHTML  

    In this paper, a novel double-sampling switched-capacitor (SC)-resonator with high performance is proposed. The quality factors of the resonators, high notch Q-value and the accurate notch frequency, are analyzed at the transfer function level. Furthermore, their effect on the quantization noise shaping in the implementation of the BP ΔΣ-modulator is explained. Discrete-time resonator topologies are discussed and the double delay resonator structure is shown to have potential to implement high performance resonators. A double-sampling switched-capacitor resonator is presented with comparisons to reported structures. The nonidealities are analyzed in the light of the preceding theoretical scrutiny. The structure is found to be very insensitive to imperfections of the analog circuits and it has a low capacitive load leading to a low power consumption. Finally, a BP ΔΣ-modulator using the proposed resonator is presented along with behavioral level simulation results. View full abstract»

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  • Region-dependent, algorithmically directed thresholds for maximum-likelihood detection of ternary PRS channels

    Publication Year: 2002 , Page(s): 775 - 783
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    This paper presents mathematical derivations for a type of maximum-likelihood sequence detector (MLSD), for decoding signals equalized to the ternary partial response fundamental polynomials - duobinary (1+D) and dicode (1-D); or part of decoders for higher-order class of partial response polynomials. Region-dependent but algorithmically directed thresholds with relatively simple updates for ternary duobinary (1+D) and dicode (1-D) channel decoders are hereby presented which depend only on state metric differences. The simplicity of the threshold updates makes the new proposition very attractive for hardware implementation. Derivations for a ternary duobinary and dicode partial-response signaling (PRS) channel decoder based on the true difference metric algorithm are included. View full abstract»

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  • On the exact realization of LOG-domain elliptic filters using the signal flow graph approach

    Publication Year: 2002 , Page(s): 770 - 774
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    Logarithmic (LOG)-domain filters can be designed using the signal flow graph (SFG) synthesis approach and an appropriate set of operators. Following the above procedure, all-pole LOG-domain filters that exactly emulate the operation of the inductor-capacitor LC ladder prototype filter can be implemented. In the case of elliptic LOG-domain filters, the transmission zeros are not precisely realized. This is due to the fact that floating capacitors are used, in order to approximately perform the required differentiations. In this paper an alternative SFG representation of the prototype system is done, in such a way that the corresponding filter configuration can be implemented using only LOG-domain lossless integrators and amplifiers. A third-order LOG-domain elliptic filter was simulated in order to confirm the validity of the proposed technique. View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope