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Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Issue 4 • Date December 1985

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Displaying Results 1 - 25 of 27
  • Foreword

    Publication Year: 1985 , Page(s): 409
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    Freely Available from IEEE
  • The PCB Connector as a Surface Mounted Device

    Publication Year: 1985 , Page(s): 530 - 534
    Cited by:  Papers (2)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB)  

    The problems and solutions relative to the design of PCB connectors for surface mounting are explored. The systems approach is discussed because surface mount technology (SMT) for connectors is largely driven by the need for minimum labor, and automated production lines. Therefore, the design must consider the application of the connectors by robots. This in turn brings about the need to consider how to package the connectors for presentation to the robot, how to identify the connector, and how the connector can be picked Up by the robot arm, consistentlY. Once on the board, the effect of large mating and unmating forces must be brought into the equation. The connector must be held down by some mechanical means, which must also be compatible with the capabilities of the robot. These problems are all explored. Answers to the design Problems are put forth, the conclusion being that all technologies are presently available to make the SMT connector a viable product family. View full abstract»

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  • TAB Versus Wire Bond-Relative Thermal Performance

    Publication Year: 1985 , Page(s): 490 - 499
    Cited by:  Papers (5)  |  Patents (1)
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    There has been a resurgence of interest in tape automated bonding (TAB) as a method of interconnection between the chip and the substrate in recent years. Proponents of TAB have claimed superior thermal performance for TAB bonded packages compared to wire bonded packages. However, little experimental evidence for such claims existed. Described are experiments and theoretical modeling done on Wire bonded and TAB bonded packages under free air, forced air, and conduction cooling for various die attach methods. For packages mounted on cold plates where \theta jc(i.e., internal thermal resistance of the package) dominates the thermal behavior of the package, TAB bonded packages were found to have slightly lower thermal resistance than wire bonded packages. For PCB- and socket-mounted packages dissipating heat in natural or forced-air cooling where \theta ca(i.e., external thermal resistance) dominates the thermal behavior of the package, TAB bonded and wire bonded packages were found to have about the same thermal performance. View full abstract»

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  • Reliability of High-Voltage LSI's Made Using the Dielectric Isolation Process

    Publication Year: 1985 , Page(s): 564 - 568
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    A high-voltage subscriber-line interface large-scale integrated (LSI) circuit with high reliability is developed. To realize 350 V blocking voltage, this high-voltage LS1 is fabricated using an epitaxial passivated integrated circuit (EPIC) dielectric isolation technology and a field plate technique. Certain instabilities, such as leakage current increase and breakdown voltage decrease, has been reduced by using an n+buried layer and a field-plate structure for a low-voltage junction in the high-voltage device. This technique produces high-voltage LSI's with long-term stability and reliability of less than 20 FIT. This is confirmed by results of a 125°C, 10 000-h operating test. It is confirmed that highvoltage LSI's made by the EPIC dielectric isolation process are as highly reliable as low-voltage conventional bipolar LSI's. View full abstract»

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  • Ball Formation in Aluminum Ball Bonding

    Publication Year: 1985 , Page(s): 559 - 563
    Cited by:  Papers (3)
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    The effects of various factors, i.e., shield gas, current density, wire polarity, and wire material, which can influence oxidation of ball surfaces were investigated. Good quality aluminum balls were found to be formed if optimum electric and shield gas conditions were employed; for example, current density \geq 2.5 GA/m2wire polarity: cathode; shield gas: Ar+H2. Good quality aluminum balls of 1.7 to 2.5 times the wire diameter could be formed by varying discharge time and/or current density. It was found that they could be obtained independently of the wire material. The relation between morphologies of aluminum balls and the degree Of oxidation was also investigated in order to examine the mechanism for obtaining a good quality bail. A close correlation was found between ball morphologies, i.e., eccentricity, sphericity, and constriction, and the degree of oxidation. The morphologies were significantly improved as the oxide film thickness was reduced. View full abstract»

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  • Miniline: Research Applied to Manufacturing

    Publication Year: 1985 , Page(s): 410 - 416
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    A "miniline" concept for solving technical problems on manufacturing lines has been successfully used on several different products. Key to this success is using fundamental science with the most advanced methods of characterization possible to analyze pieces of real product processes. Industry or university scientists simulate the production process closely by using sophisticated analytical tools appropriately · instrumented. This results in fundamental understanding of the sequence of events occurring in each process step in the production line. Understanding leads to better definition of process windows and better control of the process. Parts may be Processed on the production line or on the laboratory equipment for direct comparison of particular production steps. Teamwork among researchers and an interdisciplinary group of development and manufacturing engineers is a key ingredient to success. View full abstract»

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  • Plasma Process Induced Device Degradation

    Publication Year: 1985 , Page(s): 550 - 555
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    A new plasma-induced device degradation for silicon gate FET devices is described, namely, a negative threshold voltage shift caused by plasma etching of plasma-enhanced chemical vapor deposited silicon nitride films. Negative VTshifts from hundreds of millivolts to more than 3 V occurred in N-channel devices of 45-nm gate oxide thickness whose gates were not tied to protect diodes or diffusions. The principal cause for the VTshift was the electrostatic potential developed across the device gate region during plasma etching. The proposed mechanism model is based on impact ionization in the gate oxide; i.e., electron/hole pairs are generated in the oxide from electrons accelerated from the silicon substrate during plasma etching. The resulting holes fill interface states and traps in the oxide causing negative VTshifts. Of the three preventative techniques given, the addition of a low-capacitance dielectric between the wafer and the etcher's conductive electrode is believed to be an ideal solution. View full abstract»

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  • Electrical Characterization of Packages for High-Speed Integrated Circuits

    Publication Year: 1985 , Page(s): 468 - 473
    Cited by:  Papers (19)
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    Advances in silicon bipolar and GaAs FET technology have enabled digital circuits of medium complexity to be fabricated for operation at gigabit rates. However, signal degradation caused by the packaging of these new devices will limit their useful application. A theoretical model to help assess this problem is discussed, and its predictions are compared with results from time domain reflectometry (TDR) and network analysis measurements. Also described is a novel exlension of the TDR technique based on the use of fast Fourier transform (FFT) analysis, including the design of test fixtures and the analysis software which is run on a desktop computer. The results presented demonstrate that both the model and the FFT measurement technique accurately represent the electrical performance of all those packages tested. View full abstract»

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  • High-Reliability Solder Connection for ZIF Connectors

    Publication Year: 1985 , Page(s): 541 - 545
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    A new type of zero insertion force (ZIF) connector is proposed. In this new connector, the contact pair consists of an input/ output (I/O) pin and solder. An appropriate amount of solder fills cavities formed in the connector housing, and the position of the cavities corresponds with that of the I/O pins attached to the large-scale integration (LSI) module. The I/O pins are inserted or withdrawn, while the solder is melted. The possibility of this type of connector was examined using In-48%Sn (percent symbol stands for mass percent) solder and three kinds of surface finishes for the I/O pins; Au/Ni, Pd/Ni, and Au (very thin top layer)/Pd/Ni films. The solder was filled in the cavities formed in a glass-ceramic substrate, and electrical resistance between the I/O pin and solder was measured. A combination of the In48%Sn solder and Au/Pd/Ni film exhibits low electrical resistance even after many insertion/withdrawal cycles, indicating that these materials have suitable characteristics for the new type ZIF connector. A connector model using these materials shows low electrical resistance, below 10 m \Omega after 50 insertion/withdrawal cycles. Experimental results indicate that the new type of connector has a high potential for use as a ZIF connector for future high-density pin grid array connections. View full abstract»

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  • Imaging Latch-up Sites in CMOS Integrated Circuits Using Laser Scanning

    Publication Year: 1985 , Page(s): 556 - 558
    Cited by:  Papers (1)
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    A novel approach to using laser scanning to analyze latch-up sites in complementary metal-oxide semiconductor (CMOS) integrated circuits (IC's) has been developed. The technique employs a continuous wave (CW) laser beam scanned across a CMOS IC as the power to the IC is modulated. Signals corresponding to latch-up currents are detected with a lock-in amplifier and are used to produce a two-dimensional image of latch-up sites on a high resolution monitor. View full abstract»

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  • Current-Leakage Kinetics Across Tinned Cr/Cu Lands Having Epoxy Overlay

    Publication Year: 1985 , Page(s): 440 - 445
    Cited by:  Papers (1)
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    A leakage current between Cr/Cu conductors on a ceramic vehicle coated with an epoxy layer is described. The leakage is measured under stress conditions of temperature, relative humidity (RH), and voltage. A model is developed to project the leakage results to field conditions as a function of the stress, gap, and diffusion properties. View full abstract»

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  • Low-Stress Resin Encapsulants for Semiconductor Devices

    Publication Year: 1985 , Page(s): 486 - 489
    Cited by:  Papers (24)  |  Patents (1)
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    An innovative low-stress epoxy encapsulant was developed for large and stress-sensitive devices by the utilization of silicone modification technology. The characteristics can be explained by achieving a lower Young's modulus and thermal expansion coefficient. The low-stress level was confirmed by piezo-resistance measurement with actual results showing a definite, significant improvement against package and passivation cracks. An interesting microstructure of the new material was determined and labeled "Sea-Island" structures. View full abstract»

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  • The Effect of Joint Design on the Thermal Fatigue Life of Leadless Chip Carrier Solder Joints

    Publication Year: 1985 , Page(s): 417 - 426
    Cited by:  Papers (5)
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    The influence of solder joint shape on the reliability of solder joints formed between 84 I/O, 0.025-in (0.635-mm) pitch noncastellated leadless ceramic chip carriers and multilayer printed wiring boards has been quantified. (A castellation is a metallized radial feature on the edge of a ceramic chip carrier for interconnecting conducting surfaces or planes within or on the chip carrier. Castellations are usually on all four edges of the chip carrier. Noncastellated chip carriers may use vias instead of castellations for achieving the same interconnection.) The method is discussed by which a solder joint can be shaped to provide a substantial improvement in thermal cycle performance. Aspects of the investigation that are reported include the room temperature tensile test characterization of the stress/strain behavior of 60Sn/40Pb solder, finite element method calculations of the impact of joint shape on the deformation behavior of leadless ceramic chip carrier solder joints, mechanical shear test characterization of selected solder joint shapes, and thermal cycle testing to quantify the fatigue performance of several shaped leadless ceramic chip carrier solder joints. View full abstract»

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  • Packaging Technology for the NEC SX Supercomputer

    Publication Year: 1985 , Page(s): 462 - 467
    Cited by:  Papers (45)  |  Patents (12)
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    Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory. View full abstract»

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  • Zirconium Nitride Thin-Film Resistors With High Thermal Durability

    Publication Year: 1985 , Page(s): 512 - 516
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    A ZrN thin-film resistor is proposed as a promising heating resistor for a future thermal printing head used in high-resolution highspeed printing. The ZrN film is prepared by nonreactive sputtering with a hot-pressed ZrN target. The present method is able to control the film characteristics mainly through the nitrogen content in the sputtering atmosphere as well as achieve good reproducible results. Practical films, which have a small resistance change with temperature as well as during aging tests, are provided with resistivities of 0.5 to 5 m \Omega .cm. Thermal printing element test pieces with 16-dot/mm resolution are fabricated to examine the thermal durability of the ZrN thin-film resistor when applied to high-speed printing. The results of heat pulse life tests make clear that the elements are applicable to high-speed (a 0.3-ms duration and a 1.0-ms repetition interval) printing of excellent quality and sufficient thermal durability. View full abstract»

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  • Voltage Dependence of Activation Energy for Multilayer Ceramic Capacitors

    Publication Year: 1985 , Page(s): 517 - 524
    Cited by:  Papers (9)
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    Current-voltage and activation energy measurements can be used to probe grain boundary potential barriers. A common type of activation energy for Current conduction in a polycrystalline material is that due to the grain boundary potential barrier. Activation energy can be related directly to grain boundary barrier height. The height of this barrier depends on occupation of grain boundary states. Its decrease with applied voltage accounts for the superohmic current-voltage behavior of polycrystalline silicon and of ZnO varistors. It also accounts for positive temperature coefficient device behavior. A similar voltage dependence is reported here for barrier layer and COG type capacitors, where activation energies decrease from 0.99 to 0.44 eV and from 1.61 to 0.90 eV, respectively. Such decreases are not seen for X7R devices, even though currents are superohmic. Several mechanisms account for this. It is concluded that the grain boundary potential barrier may offer a major source of impedance to leakage current in multilayer ceramic capacitors, and its decrease may result in device failure. View full abstract»

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  • Solder Pad Geometry Studies for Surface Mount of Chip Capacitors

    Publication Year: 1985 , Page(s): 505 - 511
    Cited by:  Papers (2)
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    An optimized solder pad geometry for surface mounting chip capacitors is developed. In surface mount production poor design can cause low yields and may require expensive redesign, retooling, and reprogramming of equipment. The solder fillets were examined visually for three types of defects. The general procedure used was to surface mount capacitors onto epoxy and alumina substrates using vapor phase reflow and infrared reflow. The solder used was 60Sn/40 Pb. Capacitors used were palladium/silver frit terminated (five-sided termination) and thin-film terminated (end termination only). Visual defects observed as a function of solder pad geometry were opens, misalignment Of chips (rotation), and drawbridges. Geometry of the solder pads was seen to play an important role in the visual defects observed. Of particular importance were the overlap of the pad and the capacitor, the width of solder pads, and the extension of the solder pad outside the capacitor (in the length dimension). Capacitor sizes used were 0805, 1206, and 1210 components. View full abstract»

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  • Corrosion inhibiting lubricants for separable connectors

    Publication Year: 1985 , Page(s): 546 - 549
    Cited by:  Papers (3)
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    Microcrystalline wax by itself or in combination with polyphenyl ether inhibits corrosion, increases contact wear life, and lasts for reasonable times at higher operational temperatures. All other lubricant combinations evaluated either did not inhibit corrosion and improve wear performance or have sufficient longevity for practical contact applications. In addition to evaporative loss, lubricant mobility and absorption into the substrate cause depletion in the contact region. The wax lubricant cannot be exposed to temperatures above the melting point of the wax during processing, shipping, storage, or use. The wax becomes more mobile and reduces its effectiveness as a corrosion inhibiting layer. View full abstract»

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  • Development of Corrosion-Resistant Aluminum Alloy Wire

    Publication Year: 1985 , Page(s): 457 - 461
    Cited by:  Papers (4)
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    A study was undertaken to find a corrosion-resistant aluminum alloy wire for improving the reliability of resin-molded devices using aluminum ball bonding. Palladium (Pd) was selected to be alloyed to aluminum matrix in order to improve corrosion resistance on the basis of the passivation theory that some metals are passivated when certain noble elements are dispersed uniformly in the matrix. AI-Pd alloy wires were made containing magnesium (Mg) which was added to improve bondability between aluminum balls and aluminum electrodes. It was found that AI-Pd-Mg alloy wires exhibit outstanding corrosion resistance compared with AI-Si and AI-Mg wires in both the pressure cooker test (PCT) and another test in which the wires were dipped into a bath of boiling water together with resin powder. Intergranular corrosion was recognized in AI-Si and AI-Mg wires in PCT. AI-Pd-Mg wire hardly corroded even after 500 h of PCT. Dissolution of the wires was observed in the dipping test. However, dissolution of the AI-Pd-Mg wire is much less than that of the other wires. A good quality aluminum ball, highstrength bonding, and good looping characteristics can be realized using AI-Pd-Mg wire. It is concluded that AI-Pd-Mg wire satisfies all the major requirements of bonding wires. The corrosion protection mechanism of AI-Pd alloy was explained as the strengthening of surface protection film on the aluminum matrix by the addition of Pd. View full abstract»

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  • Stress-Induced Deformation of Aluminum Metallization in Plastic Molded Semiconductor Devices

    Publication Year: 1985 , Page(s): 427 - 434
    Cited by:  Papers (42)
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    Plastic encapsulation of large semiconductor chips has resulted in increased stress-related failures such as cracked passivation, metal deformation and delamination, cracked chips, cracked packages, and parameter shifts. The large mismatch in the coefficient of thermal expansion between the silicon chip and the plastic encapsulant is felt to be the major contributor to these failures. In an effort to minimize stress problems, many mold compound manufacturers have modified their formulations and epoxy resin chemistries. As a result, many "low-stress" mold compounds have been introduced in recent years. A procedure was developed for screening encapsulation plastics for mechanical stress on semiconductor chips. The method involves temperature cycling of molded packages containing unpassivated test chips. The degree of deformation of the metallization is used as a measure of stress on the chip. Several semiconductor grade epoxy mold compounds were evaluated with this procedure. Many of the newer low-stress epoxy formulations gave metal deformation equal to or greater than the standard formulations. One of the materials, however, yielded no observable metal deformation under the test conditions. Metal deformation is a result of shear stress acting at the chip surface, with the direction of the deformation being toward the center of the chip. Microscopic cross-sectional analysis of temperature cycled packages revealed microcracks in the plastic which appeared to have initiated at the chip edge. In most cases, the cracks were about 400/ \mu m long and thus did not reach the package surface. The microcracks appear to promote metal deformation, since they reduce the restrictions on plastic movement at the chip surface. SEM analysis was employed to determine the topography of the deformed aluminum stripes. The effects of chip size, aluminum line width, number of temperature cycles, and post-cure conditions were also determined. View full abstract»

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  • Effect of Aluminum Doping on the Electrical Properties of ZnO Varistors

    Publication Year: 1985 , Page(s): 525 - 529
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    Analysis and calculations have been made of the concentration and state of various point defects of ZnO varistors before and after donor doping at high and room temperatures using the point defect model. The results obtained show that donor doping (e.g., the doping of AI) appreciably increases the concentration of the carriers in ZnO varistors, reduces the upturn potential, and significantly lessens the dependence of the conducting behavior for large currents on sintering conditions. In particular, when the effective concentration of doped donor approaches 5 x 1017cm-3; the concentration of carriers at room temperature will in the main not vary with the change in sintering conditions and is very close to the concentration of the carriers at high temperatures. An analysis based on the energy band model shows that, owing to the effect of segregation, excessive AI doping will deteriorate the nonlinearity characteristics in the region of small current. This can be improved by quickly dropping the temperature. View full abstract»

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  • Large Copper Substrates for Surface-Mounted Components

    Publication Year: 1985 , Page(s): 481 - 485
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    The development of large and functionally complex digital semiconductor chips operating at high clock rates has been paralleled by the elaboration of novel packaging concepts to accommodate the large number of input/output ports associated with such devices, and to permit pretesting and characterization before assembly. Probably the most successful packaging approach for such chips is the ceramic leadless chip carrier (LCC) which, in addition to the requirements listed above, provides low reactance interconnects with equal path lengths for all ports. Large substrates are used in combination with LCC's and other surfacemounted components to form the final circuit. For military and other high reliability applications, the preferred substrate material is alumina, which matches the temperature coefficient of the integrated circuit (IC) package; conductors and soldering pads are applied by thick-film screening techniques. Compared to the traditional conductor materials used in thick-film hybrid fabrication (gold, silver, platinum-gold), copper offers several advantages with respect to solderability and repairability but requires more sophisticated handling and processing techniques. Since it is a relatively new technology, performance and processing data are still sparse; nevertheless copper is now used in a number of critical military applications where the requirements for solderability, repairability, thermal conductivity, and cost could not easily be met by precious metal technology. The Raytheon Company has set up in its Quincy, Massachusetts, Plant a production facility capable of manufacturing large multilevel copper motherstrates (4 inch x 5 inch) at the rate of 400 units per month, with production expected to rise to a level of 1000 units per month by mid-1985. The 30 different designs in current production are intended to receive between 60 and 80 LCC's of various sizes and configurations mounted by vapor phase reflow soldering. As many as 12 desoldering and resoldering procedures may be carried out on each board to replace defective LCC's. Each substrate requires an average of 50 screening steps, with some designs calling for 60 or more. The number of conductor layers varies from five to seven, with as many as 2000 interconnecting via- s per unit. Despite the complexity of this family of devices the overall yields have averaged 85 percent thanks to rigorous process and material controls. All procedures starting with computeraided design (CAD) artwork generation and screen manufacturing are carried out within the same plant. The circuits exhibit no bowing (potatochip effect) even without compensatory backside screening, thereby reducing final thickness and weight, and improving thermal transfer to the heat sink in the final system assembly. View full abstract»

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  • Improving Thermosonic Gold Ball Bond Reliability

    Publication Year: 1985 , Page(s): 446 - 456
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1336 KB)  

    A comprehensive study using normal probability paper to project gold wire bond reliability has been performed. Reliability projections have been made using ceramic capillaries, tungsten carbide capillaries, gold wire, gold/palladium alloy wire, three different device metallizations, nine different wire lot numbers, and seven ultrasonic power settings. The reliability projections from all of the tests were then compared to the ball shear force from each test to correlate shear force with reliability. The results indicate that several orders of magnitude increase in reliability can be achieved from using optimum wire bond parameters. The ball shear force value has also been shown to be very useful in predicting reliability and thus eliminating time consuming wire pull tests. View full abstract»

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  • Surface-Soldered Pinless Module Connector

    Publication Year: 1985 , Page(s): 535 - 540
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB)  

    Innovation in chip design and manufacture produces an ever-increasing density in packaged circuits. This demands an increase in input/output (I/O) lines from module to printed circuit card/board. Improved wireability is also needed at the printed circuit card/board levels. Surface solder of Components allows the use of smaller vias and more lines per channel to help achieve that wireability. In addition, cost per interconnection is constantly under pressure for reduction. A pinless module interconnection system is described which addresses these concerns and outlines the design features and concepts involved in its operation. The connector uses a spring beam low-energy high-contact-stress noble metal electrical contact. The connector system features wipe for improved metal-to-metal contact, and it may be used in high density I/O grid arrangements. It is shown that a low-force, surface-soldered contact system can be used to produce a reliable high-density interconnec- tion. View full abstract»

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  • High- Accuracy Die-Bonding Technology for LED Array

    Publication Year: 1985 , Page(s): 500 - 504
    Cited by:  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    A die-bonding technology was developed and includes 1) high-accuracy, full cutting of a light-emitting diode (LED) array on a GaAsP substrate with a dicing saw; 2) screen printing of a B-stage curing, Ag-filled epoxy resin on an alumina ceramic snbstrate on which a thickfilm gold conductor is formed; 3) loading and fixing of the aforementioned ceramic substrate onto the die-bonder heater stage; and 4) die bonding by maintaining the spatial position of the LED array with five tools of the die bonder until the epoxy resin is thermally cured. The highly accurate positioning and stable conductivity of the die bond is ensured by reducing the dispersion of positional error between the LED array and ceramic substrate to within ± 10 \mu m and providing stable ohmic contact characteristics between the LED array and ceramic substrate. View full abstract»

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Aims & Scope

This Transaction ceased production in 1993. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope