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Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Issue 3 • Date September 1983

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  • Editorial

    Publication Year: 1983 , Page(s): 225
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    Freely Available from IEEE
  • Guest Editor's Comments

    Publication Year: 1983 , Page(s): 226
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  • A New Chip Carrier for High Performance Applications: Integrated Decoupling Capacitor Chip Carrier (IDCCC)

    Publication Year: 1983 , Page(s): 290 - 297
    Cited by:  Papers (3)
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    The impact of inductance has rarely been considered in semiconductor Packaging. This is the reason for using the capacitor in the first place: it is a small, local energy reservoir for those current transients which cannot go back to the power supply without causing unacceptahly large voltage drops (V = L di/dt). Since 1978 a new chip carrier with integrated deeoupling capacitor (IDCCC) has been studied. T]he capacitor is located inside the bottom layer in a threelayer or a single-layer chip-carrier. The ceramic package previous!y used had a nonactive bonding pad layer: with our IDCCC, this layer (standard thickness is 25 mils) is made out of several layers from 3 to 5 mils with the electrodes. The technology is about the same as the one used in multilayer ceramic capacitors. This capacitor is located just under the device, but not under the conductor I/O to avoid a parasitic capacitive coupling. With the coming of leadless and leaded full array chip carriers such as pin grid array, we applied the same concept with a Capacitor inside the cap. The results with different current-pulse signals show the effects of the capacitor's inductance, resistance, and capacitance. The main specifications of this new chip carrier will be presented. In addition to improving speed and electrical Performances, the IDCCC allows an increase in density and in reliability level. View full abstract»

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  • High Pinout IC Packaging and the Density Advantage of Surface Mounting

    Publication Year: 1983 , Page(s): 298 - 304
    Cited by:  Papers (1)
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    The packaging industry has been addressing the high pinout integrated circuit (IC) packaging issue in recent years. The specific solutions adopted have varied on a case by case basis and appear to he based on meeting a combination of objectives: 1) meeting needs with a workable short term evolution of the current packaging technology, and 2) consistency with long term objectives. The former is usually emphasized over the latter. Extensions of conventional through-hole packages are more directly compatible with the Present day dual-in-line package (DIP). Surface mounted packages are expected to yield higher board level interconnection densities in the long term. A procedure [7] is utilized which incorporates the Schmidt routability analysis methodology [5] to compute packaged circuit pack level gate densities as a function of various IC, IC package, and printed wiring board (PWB) technology options. The PWB technology options include multilayer approaches spanning a range of combinations of feature sizes and via types. Packaged board level gate densities are compared for state-of-the-art gate array chips packaged in the following IC package options: 1) through hole pin grid array, 2) surface mount pad grid array, and 3) surface mount JEDEC-style chip carriers. The paper will conclude that for the range of interconnection technologies considered there are significant inherent density advantages to surface mounted components such that it is worthwhile overcoming some incompatibility with the ubiquitous DIP package. View full abstract»

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  • Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling

    Publication Year: 1983 , Page(s): 232 - 237
    Cited by:  Papers (103)
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    An ana1ytica1 method is described which provides estimates to first order of the number of either power or envirnnmenta1 cyc1es 1eading to so1der joint fai1ure. Vari0us parameter variations such as so1der joint height, ceramic chip carrier (CCC) size, printed c1rcuit substrate (PCS) materia1, etc. are investigated and discussed and samp1e estimates for a 0.65 x 0.65-in CCC are given. View full abstract»

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  • Shallow Doping in Silicon

    Publication Year: 1983 , Page(s): 309 - 313
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    In recent years liquid-state diffusion by laser melting has been instituted in device manufacture; and annealing of doped polysilicon and ion implantation damage by various lasers and incoherent radiation sources have been investigated. Continuous wave (CW) laser annealing was shown to be superior in the reduction of polysilicon sheet resistance due to increase in grain size. Incoherent radiation sources appear to be practical for dopant activation with mimimum redistribution. The conventional furnace technology continues to play an important role while new technologies are introduced to complement it. These various technologies for shallow doping (> 1 µm) in silicon are reviewed in terms of cost, throughput, special process requirements, dopant activation, dopant profile shift, and device characteristics. View full abstract»

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  • Improved Electrical Performance Required for Future MOS Packaging

    Publication Year: 1983 , Page(s): 283 - 289
    Cited by:  Papers (12)  |  Patents (5)
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    High speed integrated circuit (IC) families and the demands which these devices place on interconnection and power systems are compared, concluding that new materials, components, and packaging techniques are required to provide a nonlimiting electrical environment for high performance systems using metal-oxide semiconductor (MOS) technologies. View full abstract»

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  • Direct Attachment of Leadless Chip Carriers to Organic Matrix Printed Wiring Boards

    Publication Year: 1983 , Page(s): 227 - 231
    Cited by:  Papers (3)
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    A test program was performed that compares the reliability of various leadless chip carrier (LCC) solder joint configurations under conditions of temperature cycling from -55 to +125°C. Since there is a coefficient of thermal expansion mismatch between the ceramic body of the LCC (6 ppm/°C) and that of an epoxy-glass printed wiring board (15 ppm/°C), it was of interest to determine the optimum solder joint configuration that results in maximum reliability after extensive exposure to temperature extremes. This configuration was determined to be the one that results in a 45° solder fillet; consequently, the distance the printed wiring board (PWB) pad extends beyond the edge of the LCC is a critical requirement. For an 18 pad LCC, this distance is 40 mils. Information on the use of various substrates for leadless chip carriers is also discussed. View full abstract»

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  • Thermal Studies on Pin Grid Array Packages for High Density LSI and VLSI Logic Circuits

    Publication Year: 1983 , Page(s): 246 - 256
    Cited by:  Papers (24)
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    The highest speed silicon logic chips are currently made using the emitter coupled logic (ECL) bipolar technology which inherently dissipates more power than other logic families. Recent developments include a macrocell array (MCA 2TM) logic chip dissipating up to 12 W of power over 0.47 cm2and there are plans to develop a technology chip dissipating 10 W of power over an area of 1.03 cm2, both to be used in high performance applications. It is essential that the packages housing these chips, have good thermal and electrical characteristics to fully realize the potential of these chips. Extensive computer-based thermal modeling and experimental studies were performed to design a high thermal performance ceramic pin array package utilizing the cavity down approach. Single-layer alumina, muitilayer alumina, and muitilayer beryllia-alumina composite packages were studied. Both unidirectional and omnidirectional heatsinks were computer modeled, designed, and tested in a wind tunnel. Power transistor and MCA 2 logic chips were used to simulate the power levels. Both parametric and infrared microscopic methods were used to determine the junction temperatures. Finite difference modeling calculations were performed for various package configurations and compared with experimental results. The work has resulted in packages meeting the thermal requirements. A beryllia-alumina composite substrate package with an omnidirectional heatsink is chosen to house the 12 W power dissipating MCA 2 chip. It has a measured value of 3.3°C/W for \Theta jain 750 linear feet per minute (3.8 m/s) air flow at sea level. An all alumina substrate pin array package with an omnidirectional heatsink is chosen as the technology package to house the 10 W power chip. It has a measured value of 5.1°C/W for \Theta jain 1000 lfm (5.1 m/s) air flow at sea level. View full abstract»

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  • Optical Coupling in Fiber Optics Packages with Surface Emitting LED's

    Publication Year: 1983 , Page(s): 334 - 342
    Cited by:  Patents (1)
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    The optical coupling performance of two fiber optics emitter packaging styles is determined into five large-core-diameter [ \geq 100 µm) optical fibers with varying numerical apertures (NA). One package contains a short fiber coupled to a high index spherical lens positioned accurately between the LED and the fiber. The other package is fiberless, utilizing a high index lens bonded accurately to the LED using an alignment ring technique, and projects light through the package's glass window to intercept the system fiber. Computer modeling studies have been combined with the manufacture and analysis of actual packages to investigate the optimum lens parameters for both packaging styles. Experimental and modeling studies suggest that for optical fibers with NA's \leq 0.20, the fiberless and short-fiber packages couple equivalent optical powers into fibers with diameters \leq 200 µm. For larger diameters, the fiberless package is somewhat superior. With high NA fibers ( \geq 0.30), however, the short-fiber package is clearly superior for fiber diameters up to 200 &microm, and equivalent for diameters greater than 200 µm. The excellent performance of the fiberless package is achieved because the alignment ring technique provides not only the desired alignment accuracy, but also yields a reproducible LED-to-lens spacing. View full abstract»

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  • Analysis of Surface Mount Thermal and Thermal Stress Performance

    Publication Year: 1983 , Page(s): 257 - 266
    Cited by:  Papers (23)
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    Ongoing analysis of leadless ceramic devices surface mounted to epoxy-glass is described. Finite element (FE) model results for thermal resistance as a function of airspeed, carrier size and spacing, and heatsinking are given. An overview of the thermal stress problem, emphasizing fatigue test design, is presented. The rationales used in choosing thermal cycle amplitudes, methods of heat transfer, definitions of failure, test frequency, and desired cycles to failure are compared to current industry practice and discussed in the context of their impact on test results. View full abstract»

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  • Structural Characterization of Processed Silicon Wafers

    Publication Year: 1983 , Page(s): 314 - 322
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    Two techniques, chemical etching and X-ray diffraction, for the characterization of process-induced defects in silicon wafers are illustrated. The types of etchants used to reveal various defects are reviewed. The use of a Lang camera for the measurements Of bulk defects and mechanical stress in silicon wafers is presented. Examples are given demonstrating the use of these two techniques: to monitor the type and density of defects as well as wafer stress in several key steps during wafer processing. Process-induced defects which limit the device yield are also presented. View full abstract»

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  • Corrosion of Gold-Coated Contact Materials Exposed to Humid Atmospheres Containing Low Concentrations of SO2and NO2

    Publication Year: 1983 , Page(s): 349 - 355
    Cited by:  Papers (1)
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    Corrosive atmospheres containing SO2, NO2, and SO2+ NO2(NO2:0.5, SO2:0.6 ppm) have been investigated and their corrosive effects on gold-plated brass were studied. The thickness of the gold coating was 0.3, 1.0, or 2.0 µm. Corrosive gas atmosphere containing NO2(0.5 ppm) caused corrosion sites already at low relative humidity, (40 percent) and the corrosion products contained no nitrogen compounds, just oxides. SO2-containing atmospheres were aggressive at relative humidities (RH) above 60 percent and did not cause as many corrosion sites per square centimeter as did NO2. A mixed-gas atmosphere containing both SO2and NO2(0.6 + 0.5 ppm) caused the formation of suiphuric acid on the surface. This reaction was catalysed by the gold surface. This long lived liquid surface layer acts as a corrosive electrolyte. No nitrogen-containing corrosion products were produced in this atmosphere either. Atmospheric corrosion experiments have been performed with gold-coated brass used in contacts in electrical circuits. The electroplated gold coatings were 0.3, 1.0, and 2.0 µm thick, respectively. The base metal consisted of 73 percent Cu, 23 percent Zn, 3.4 percent Al, and 0.4 percent Co. The corrosive atmospheres studied contained SO2or NO2in air with different relative humidities (RH). Mixed-gas atmospheres conraining both NO2and SO2have also been investigated. At low humidities NO2 was the more aggressive gas, causing pore corrosion at 40 percent RH, while SO2mainly caused attacks at humidities of 60 percent or more. The corrosion products consist of Cu- and Zn-oxides or hydroxides in NO2atmospheres and mainly Cu- and Zn-suiphates in SO2atmospheres. At all relative humidities studied here, a mixed-gas atmosphere containing both SO2and NO2caused a surface-layer consisting of sulphuric acid. The surface layer became visible after only a couple of hours exposure. Thus, at sub-ppm concentrations of SO2and NO2the gold-coated surface seems to catalyse the formation of sulphuric acid. The formation of sulphuric ac- id decreases as the surface becomes covered with acid. View full abstract»

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  • The Effect of High Dissipation Components on the Solder Joints of Ceramic Chip Carriers Attached to Thick Film Alumina Substrates

    Publication Year: 1983 , Page(s): 237 - 245
    Cited by:  Papers (3)
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    The effects of power cycling and powered high temperature storage on chip carriers solder attached to thick film alumina substrates are compared with those of conventional temperature cycling and high temperature storage. Although the high temperature storage tests gave a similar deterioration in torque strength compared with unstressed controls, power cycling produced dramatically lower values than chamber temperature cycling with the same upper ternperature. The power cycling failure mechanism is seen to be a direct result of the thermal gradient changes between the chip carrier and the substrate resulting in plastic deformation and subsequent fatigue cracking. Possible solutions to the problem are reviewed. View full abstract»

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  • High Thermal Conduction Package Technology for Flip Chip Devices

    Publication Year: 1983 , Page(s): 267 - 271
    Cited by:  Papers (6)  |  Patents (1)
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    The technology of new packages with high thermal conduction performance, simplified structure, and also high reliability for flip chip devices is described. In order to obtain high thermal conduction, a thermal conduction plate is individually bonded to the back surface of a large-scale integrated (LSI) chip by soft solder and is arranged in close proximity to the inner surface of the cap, when the chip is assembled together with the cap and substrate. The cavity is then filled with a gas which has a high thermal conductance characteristic. As a result, a large part of the heat is effectively drawn off from the back side of the chip to the air-cooling fin through the plate and across the narrow gap filled with the gas. A series of experiments were conducted on a single chip package and a nine chip multichip module. These tests indicated a junction-to-fin thermal resistance of 3.2°C/W for the single chip package and 4.8°C/W as a worst case in the module. In addition a computer model analysis for thermal conduction was studied using a program named TNET-2. It was found that the calculated values corresponded closely to the measured data. More detailed descriptions of packages and results of studies are presented and discussed here. View full abstract»

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  • Electrical Design of a High Speed Computer Packaging System

    Publication Year: 1983 , Page(s): 272 - 282
    Cited by:  Papers (15)  |  Patents (2)
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    A methodology for optimizing the design of an electrical packaging system for a high speed computer is described The pertinent parameters are first defined and their sensitivities are derived so that the proper design trade-offs can ultimately be made. From this procedure, a set of rules is generated for driving a computer-aided design (CAD) system. Finally there is a discussion of design optimization and circuit and package effects on machine performance. View full abstract»

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  • Design of a High Performance DIP-Like Pin Array Package for Logic Devices

    Publication Year: 1983 , Page(s): 305 - 308
    Cited by:  Papers (2)
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    Pin array packages offer package sizes which are much smaller than their dual in-line package (DIP) equivalent. Pin array packages are also through hole mountable. A pin array package is described which is DIP-like in that it is rectangular but the input/ output (I/O) pins do not fully populate its base. The package is a co-fired tungsten metallized multilayer ceramic package with 104 I/O's yet is only 1.16 in wide by 1.88 in long. Dual tier wire bond ledges are used to minimize wire bond lengths which also enhances electrical performance. This package is used in systems where many leads must switch simultaneously onto a heavily loaded bus. Such switching may result in considerable electrical noise. To meet noise requirements the package had to have the lowest possible ground impedance. This was accomplished by dedicating 20 percent of all pins to power and ground and by strategically positioning them on the package. Power and ground planes were also placed within the layered ceramic package to further lower the ac ground impedance. Finally, these planes were arranged to provide nearly 1000 pF highquality built-in filter capacitance. Noise is further reduced by minimizing crosstalk within the package. The presence of ground planes helps lower interlead crosstalk by factors of three to ten. Resistance and capacitance loading of the signal paths are designed to be acceptably low. A simple packaging change allows all the signal nets to be electrically probed from the top of the package. The package, depending upon its configuration and use of heat sinks, also has the capability of handling high power integrated circuits (IC's). View full abstract»

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  • Effect of HCl and Cl2on Pd Inlay Coupons and Pd Connector Contacts

    Publication Year: 1983 , Page(s): 343 - 348
    Cited by:  Papers (2)
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    Field exposure studies indicate that a resistive palladium chloride film may grow on Pd coupons when the ambient contains both high relative humidity (RH) and chlorine. This behavior raises a concern about the use of palladium in separable connectors. Most connectors are shielded systems, and the contacts are subject to wipe on mating. Therefore contact resistance probe measurements on coupon surfaces may not be representative of the behavior of connector contacts. A study on a moderately shielded connector system was initiated to compare the effects of chlorine and HCl vapors in high relative humidities on connectors with the effects on coupon surfaces. A number of material combinations including Pd against Pd, Pd against gold, and 60Pd40Ag against gold were tested in the study. It is shown that the high contact resistance values measured on the coupons are not representative of the contact resistance changes detected on connector contacts subjected to an accelerated aging treatment in the mated condition. The changes in contact resistance are much lower on connector contacts than on coupons. Palladium and 60Pd40Ag against gold are much superior in performance to Pd against Pd when exposed to Cl2environments. Exposure of mated connector contacts to HCl at high relative humidity results in little degradation of contact resistance compared to chlorine exposure. View full abstract»

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  • Quality Control Techniques for "Zero Defects"

    Publication Year: 1983 , Page(s): 323 - 328
    Cited by:  Papers (8)
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    Everyone is being exposed to the "zero defects" philosophy which establishes zero as a goal. This will not be achieved overnight but approached over time by continually striving to reduce targets. What kind of techniques are needed to assure zero defects? What constitutes an out-of-control situation? An attributes control chart conveys little information at or near zero defects. Assuring zero defects through sampling inspection leads to infinite samples or 100 percent inspection, assuming 100 percent inspection efficiency (the latter rarely exists, and efficiency probably gets worse at lower defect levels). Obviously, some new approaches to quality control (QC) techniques will be necessary at zero defects. One old standby is the variables control chart, \overline {X} and R, but with the specification at least five standard deviations from the average. Thus one route to zero defects is a properly chosen specification. However if attributes data must be used, the standard p and u charts are not very useful. Perhaps a control chart that plots the number of good items between defects on a logarithmic scale to accommodate large numbers can be used, establishing upper and lower limits on the number of items between defects. Another problem area at zero defects is sampling inspection to assure targets. Following the approach above on good items between defects, the number of accepted lots between rejected lots can be a criterion. Sample sizes can be related to lot sizes as in MIL-STD-105D. If rejected lots come too close together, a procedure can be established requiring process shutdown until the problems are resolved. This will help promote the "making it right the first time" philosophy necessary to achieve zero defects. View full abstract»

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  • Focused Ion Beams in Microelectronic Fabrication

    Publication Year: 1983 , Page(s): 329 - 333
    Cited by:  Papers (1)
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    For more than 20 years the designers and fabricators of integrated circuits and microstructure devices have strived toward smaller features as a means of achieving higher packing density, better performance, and lower cost. The new field of microlithography has emerged as a result of these pressures. The results of these efforts are a wide array of advanced development and production techniques using photooptics, electrons, and X-rays as energy sources for pattern generation and replication. Over the past 3-4 years a new technique, focused ion beam lithography, has emerged as a challenger to these lithography tools for very large-scale integration (VLSI) research and production applications. A number of significant advantages exist when using focused beams in microelectronic fabrication that are not available in the technologies mentioned above. For example, the focused ion beam (FIB) may allow manufacturers to eliminate many of the process steps associated wish conventionai implantation since FIB implants can be performed without lithography and chemical processes. Special implant steps can also be done that are neither practical nor even possible with conventional photomasking techniques. View full abstract»

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Aims & Scope

This Transaction ceased production in 1993. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope