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Circuits and Systems, IEEE Transactions on

Issue 7 • Date July 1981

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Displaying Results 1 - 15 of 15
  • Guest editorial

    Publication Year: 1981 , Page(s): 617
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    Freely Available from IEEE
  • Comments on "Computer Generation of Trees and Co-Trees in a Cascade of Multiterminal Networks

    Publication Year: 1981 , Page(s): 747 - 748
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    The problem of efficient generation of all trees has been considered in the above paper' by Chen [1]. The method is to decompose the original graph into several components and determining appropriate subgraphs in each component and then combining these subgraphs to obtain the desired results. We show that this method has an undesirable feature, which is the duplicate generation of some trees. Therefore, Theorem 4 of the paper [1] must be corrected. The definitions of all symbols will not be redefined here; we refer to Chen's original paper for detailed treatment. View full abstract»

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  • Fast Digital Filters with Low Round-Off Noise

    Publication Year: 1981 , Page(s): 716 - 723
    Cited by:  Papers (25)
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    A novel approach to the realization of fast and efficient IIR digital filters is presented. The realization is based on recently introduced state-space structures and retains and enhances their low noise and sensitivity properties while reducing the number-of-required multiplications. This permits the implementation of higher order optimal forms requiring only 1.34 to 1.65 times the number of multiplications used in the direct form (well known for 'its poor coefficient sensitivity and high output noise levels). The high inherent parallelism of the state-space structure is also further enhanced by the proposed fast digital filter (FDF). The resulting block-processing algorithm is suitable for high speed implementation of digital filters on parallel processing systems. These systems employ fast and efficient techniques, such as distributed arithmetic or multimicroprocessor techniques, to perform the required computation of the long-independent inner products. In addition to low quantization noise, the FDF structure has other desirable properties including low sensitivity and improved limit cycle behavior. For output decimating IIR filters additional savings in the number of multiplications is achieved with the proposed structure. View full abstract»

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  • Synthesis of the lossless reciprocal three-port based on a canonic form of its scattering matrix

    Publication Year: 1981 , Page(s): 736 - 744
    Cited by:  Papers (3)
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    The canonic form of the three-port scattering matrix is deduced from the relations expressing the constraints of reciprocity and losslessness. One gives a particular construction of the denominator of the entries, which allows to solve the divisibility conditions resulting from the basic equations. The necessary and sufficient conditions are given which allow to synthesize the three-port as three two-ports connected in parallel with a shunt lossless impedance at the common port. View full abstract»

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  • Large moduli multipliers for signal processing

    Publication Year: 1981 , Page(s): 731 - 736
    Cited by:  Papers (40)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    The residue number system has been recently shown to be a viable signal processing media. However, it does possess limitations. One of the most serious is overflow prevention through magnitude scaling. One method of overcoming this defect is to increase the dynamic range of the numbering system. To this end a new high-speed large moduli multiplier has been developed. The multiplier is the result of combining the quartersquared algorithm with recent breakthroughs in device technology. As a result, equivalent 18-bit full precision products can be obtained at a pipelined rate of 28.5 \times 103 multiplies per second. View full abstract»

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  • Computer-aided analysis of switched-capacitor filters

    Publication Year: 1981 , Page(s): 681 - 692
    Cited by:  Papers (6)
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    A technique is presented for computer-aided analysis for a class of switched-capacitor (SC) circuits that can be partitioned into elementary subnetworks. This new approach is distinctly different from other published techniques, because, rather than striving for complete generality, it incorporates features that are specifically needed in practical SC circuits in order to produce an efficient algorithm for machine computation. The analysis technique is formulated in the time and frequency domains and a user-oriented program (scAP) is described that implements this technique. In addition, sensitivity analysis is also formulated for this new approach. View full abstract»

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  • A design methodology and computer aids for digital VLSI systems

    Publication Year: 1981 , Page(s): 634 - 645
    Cited by:  Papers (54)
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    The current status of a research program at Carnegie-Mellon University aimed at the formulation of a hierarchical design methodology for digital VLSI circuits is described. In addition, this paper describes a set of computer aids which supports this methodology. One of the goals of this work is to provide a design environment which allows for a significant reduction in time between the initial concept of a complex digital system and the generation of masks. Another goal is to allow the designer to efficiently explore a number of design alternatives. View full abstract»

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  • Stochastic optimization in system design

    Publication Year: 1981 , Page(s): 702 - 715
    Cited by:  Papers (17)
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    The nonlinear optimization problem and statistical design problem can both be formulated as a region search problem. In this paper, we present a stochastic optimization process, suitable for optimizing functions of a certain measure over generalized regions in R^n . Conditions for an optimal process are discussed, and examples of a wide range of different optimization problems are given. These include the optimization of constrained, discontinuous and random functions in both discrete and continuous variable space. Design centering and tolerancing of large size systems subject to environmental disturbances are also treated. View full abstract»

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  • Statistical design centering and tolerancing using parametric sampling

    Publication Year: 1981 , Page(s): 692 - 702
    Cited by:  Papers (76)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1232 KB)  

    A new statistical circuit design centering and tolerancing methodology based on a synthesis of concepts from network analysis, recent optimization methods, sampling theory, and statistical estimation and hypothesis testing is presented. The method permits incorporation of such realistic manufacturing constraints as tuning, correlation, and end-of-life performance specifications. Changes in design specifications and component cost models can be handled with minimal additional computational requirements. A database containing the results of a few hundred network analyses is first constructed. As the nominal values and tolerances are changed by the optimizer, each new yield and its gradient are evaluated by a new method called Parametric sampling without resorting to additional network analyses. Thus the most costly phase of statistical design,-statistical simulation, may be carried out only once, which leads to considerable computational efficiency. Equivalent or superior designs for intermediate size networks are obtained with less computational effort than previously published methods. For example, a worst-case design for an eleventh-order Chebychev filter gives a filter cost of 44 units, a centered worst-case design reduces the cost to 18 units and statistical design using Parametric sampling further reduces the cost to 5 units (800 analyses, 75 CPU seconds on an IBM 370/158). View full abstract»

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  • VLSI design automation activities at M.I.T.

    Publication Year: 1981 , Page(s): 645 - 653
    Cited by:  Papers (4)
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    A large part of the M.I.T. research program in very large-scale integrated circuits (VLSI) deals with design automation. Industry today is facing a "design crisis" that requires substantial advances in the state of the art in design aids. University.research such as that at M.I.T. is aimed at making such advances. The design of an integrated circuit is viewed as a series of transformations among various domains of representation for the design. Many computer tools which assist in those transformations have been developed at M.I.T. There appear to be two new design methodologies emerging which are radically different from design styles currently in use in industry. View full abstract»

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  • A structured design methodology and associated software tools

    Publication Year: 1981 , Page(s): 618 - 634
    Cited by:  Papers (21)
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    The problems encountered designing very large scale integrated circuits (VLSI) are fundamentally different from the problems encountered in the design of small scale integrated circuits. The differences require a new methodology of design for the new large scale circuits, and the new design methodology requires a new set of tools. The computer-aided design work at Caltech has progressed from a recognition of the inherent differences and has produced a new design methodology and a set of tools which attack the new problems in integrated circuit design. View full abstract»

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  • Suppressing limit cycles in digital incremental computers

    Publication Year: 1981 , Page(s): 723 - 730
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    This correspondence examines the sources of limit cycle oscillations in Digital Incremental Computers and proposes several different methods for their suppression. A theoretical analysis is performed based on considering the effects of noise injected at the truncation points of the system and the results are verified by extensive simulation. View full abstract»

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  • Stanford overview in VLSI research

    Publication Year: 1981 , Page(s): 654 - 665
    Cited by:  Papers (3)
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    The Stanford University environment provides an unique combination of systems applications coupled with a state-of-the-art IC fabrication facility. Tools for VLSI design are being developed in concert with the. evolution of chip designs--the largest design to date contains more than 10000 transistors. Design methodologies are discussed as well as specific tools and approaches for IC synthesis, layout, and analysis. Recent results of a database experiment are presented. In addition, examples of specific system architecture experiments are considered. View full abstract»

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  • On the stability of digital filters designed using the concept of generalized-immittance convertor

    Publication Year: 1981 , Page(s): 745 - 747
    Cited by:  Papers (11)
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    A method for designing wave digital filters using the concept of generalized-immittance convertor has been reported recently by Antoniou and Rezk. In this paper is derived a stability criterion for this new type of filter. It is shown that the requirement for ensuring the absence of limit cycles in these filters is the same as the one proposed by Fettweis and Meerkcötter for the conventional wave digital filters. View full abstract»

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  • Design aids for VLSI: The Berkeley perspective

    Publication Year: 1981 , Page(s): 666 - 680
    Cited by:  Papers (15)  |  Patents (1)
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    Computer aids for integrated circuit (IC) design have been an integral part of the Berkeley IC program since its inception in the early 1960's. While our initial work concentrated on the development of simulation programs, such as SPICE2 and SPLICE, we are currently developing an integrated design system for VLSI circuits. The system is based on 1) the use of dedicated design stations, connected among themselves and to peripheral equipment via a high-speed computer network, and 2) a portable operating system framework for the integration of a set of design programs. This paper describes our ongoing research in the area of layout design and verification, simulation, synthesis, and optimization for VLSI design. View full abstract»

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