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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 6 • Date Jun 2002

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Displaying Results 1 - 10 of 10
  • A fast implementation of correlation of long data sequences for coherent receivers

    Publication Year: 2002 , Page(s): 430 - 433
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB)  

    Coherent reception depends upon matching of phase between the transmitted and received signal. Fast convolution techniques based on fast Fourier transform (FFT) are widely used for extracting time delay information from such matching. The latency in processing a large data window of the received signal is a serious overhead for mission critical real time applications. The implementation of a parallel algorithm for correlation of long data sequences in multiprocessor environment is demonstrated here. The algorithm does processing while acquiring the received signal and reduces the computation overhead considerably because of inherent parallelism. View full abstract»

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  • Simultaneous voltage scaling and gate sizing for low-power design

    Publication Year: 2002 , Page(s): 400 - 408
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (350 KB) |  | HTML iconHTML  

    This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this application, and propose algorithms for single voltage-scaling, single gate-sizing, and their simultaneous manipulation. We target a globally optimal solution by showing how the power optimization is related to the maximum-weighted-independent-set (MWIS) problem. Experimental results on a set of benchmark circuits show that the simultaneous voltage-scaling and gate-sizing generates maximum power reduction. The average power savings range from 23% to 57% over all tested circuits, depending upon the circuit topology, underlying gate library and specific supply voltages. View full abstract»

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  • A new identification approach for FIR models

    Publication Year: 2002 , Page(s): 439 - 446
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (341 KB) |  | HTML iconHTML  

    The identification of stochastic discrete systems disturbed with noise is discussed in this brief. The concept of general prediction error (GPE) criterion is introduced for the time-domain estimate with optimal frequency estimation (OFE) introduced for the frequency-domain estimate. The two estimation methods are combined to form a new identification algorithm, which is called the empirical frequency-domain optimal parameter (EFOP) estimate, for the finite impulse response (FIR) model interfered by noise. The algorithm theoretically provides the global optimum of the model frequency-domain estimate. Some simulation examples are given to illustrate the new identification method. View full abstract»

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  • Palmo: pulse-based signal processing for programmable analog VLSI

    Publication Year: 2002 , Page(s): 379 - 389
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    This paper presents novel signaling and circuit techniques for the implementation of programmable analog and mixed signal very large scale integration (VLSI). The signaling technique uses pulsewidth modulated digital signals to convey analog signal information between programmable analog cells. A circuit for a generic programmable analog cell is introduced and is analyzed for harmonic distortion performance. The equivalence of the cell to a switched-capacitor (SC) Miller integrator is proven. Voltage- and current-mode (CM) implementations of the generic programmable analog cell are introduced; an elegant-fast current controlled comparator is presented, and results from working analog VLSI implementations provided. View full abstract»

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  • An integrated CMOS PLL for low-jitter applications

    Publication Year: 2002 , Page(s): 427 - 429
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (213 KB) |  | HTML iconHTML  

    This brief presents a fully integrated integer-N frequency synthesizer with a frequency-tuning range from 2.4 to 2.9 GHz and root-mean-square (rms) jitter below 2.5 ps over 350 MHz. The employed architecture using an inductance-capacitance (L-C) oscillator with two control inputs combines a wide tuning range with a low noise sensitivity. Potential applications include clock generation in microprocessors and clock recovery in fiberoptic receivers. View full abstract»

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  • High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic

    Publication Year: 2002 , Page(s): 434 - 439
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (365 KB) |  | HTML iconHTML  

    In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-μm CMOS technology show that PDL with speed-enhanced skewed static (SSS) look reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%. View full abstract»

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  • Calibration of parallel ΔΣ ADCs

    Publication Year: 2002 , Page(s): 390 - 399
    Cited by:  Papers (12)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (341 KB) |  | HTML iconHTML  

    A method of calibrating the gain and offset of each channel in parallel ΔΣ analog-to-digital converters (ADCs) is presented. It uses a digital ΔΣ modulator to perform fast and simple offline calibration. Simulations performed on the converter show greater than 30-dB reduction in unwanted tones when this calibration algorithm is used on an eight-channel second-order time-interleaved parallel converter with a 1% gain mismatch and 1-mV offset mismatch. The calibration method is general and can be used with any parallel ΔΣ ADC including time-interleaved- and Hadamard-modulation-based architectures. View full abstract»

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  • An FSK demodulator for Bluetooth applications having no external components

    Publication Year: 2002 , Page(s): 373 - 378
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (246 KB) |  | HTML iconHTML  

    An injection-locked oscillator in combination with a phase detector is shown to make a very effective frequency-shift keying (FSK) demodulator for Bluetooth applications. The dynamic behavior allows automatic tuning from outside the locking range. Two tuning methods are described which eliminate the need for external components, allow fast tuning and can handle low-frequency data. A cancellation technique is used which minimizes filtering requirements. The demodulator was fabricated in a bi-complementary metal-oxide-semiconductor (BiCMOS) technology with Leff = 0.25 μm. The die area was 0.09 mm2 and the current consumption was 0.8 mA with a supply voltage of 2.8 V. View full abstract»

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  • Closed-form design of maximally flat IIR half-band filters

    Publication Year: 2002 , Page(s): 409 - 417
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (339 KB) |  | HTML iconHTML  

    Half-band (HB) filters are of great importance and are often used in multirate digital signal processing systems, filter banks and wavelets. In this paper, a new closed-form expression for the transfer function of the maximally flat (MF) infinite-impulse response (IIR) HB filters is presented. The filter coefficients are directly obtained by solving a linear system of Vandermonde equations that are derived from the maximal flatness conditions. The proposed IIR half-band filters are more general than the existing half-band filters, because they include the conventional finite-impulse response (FIR) half-band filters with exactly linear phase, the generalized FIR half-band filters with approximately linear phase and the all-pass-based IIR half-band filters, as special cases. Furthermore, the causal stable IIR HB filters and the IIR HB filters with exactly linear phase can be realized also. Finally, some design examples are presented to demonstrate the effectiveness of the proposed IIR HB filters. View full abstract»

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  • A new architecture for implementing pipelined FIR ADF based on classification of coefficients

    Publication Year: 2002 , Page(s): 418 - 426
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB) |  | HTML iconHTML  

    In this paper, we propose a new method for implementing pipelined finite-impulse response (FIR) adaptive digital filter (ADF), with an aim of reducing the maximum delay of the filtering portion of conventional delayed least mean square (DLMS) pipelined ADF. We achieve a filtering section with a maximum delay of one by simplifying a pre-upsampled and a post-downsampled FIR filter using the concept of classification of coefficients. This reduction is independent of the order of the filter, which is an advantage when the order of the filter is very large, and as a result the method can also be applied to infinite impulse response (IIR) filters. Furthermore, when the proposed method is compared with the transpose ADF, which has a filtering section with zero delay, it is realized that it significantly reduces the maximum delay associated with updating the coefficients of FIR ADF. The effect of this is that, the proposed method exhibits a higher convergence speed in comparison to the transpose FIR ADF. View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope