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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 1 • Date Jan 2002

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Displaying Results 1 - 9 of 9
  • Sampled-function weighted order filters

    Publication Year: 2002 , Page(s): 1 - 10
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (420 KB) |  | HTML iconHTML  

    In this paper, a new type of L-filter, called a sampled-function weighted order (SFWO) filter is proposed. The coefficients of this filter are samples of a bounded real-valued function. This weighting function is derived for any given noise distribution by examining the asymptotic behavior of the corresponding L-filter coefficients. SFWO filters designed in this way constitute a good compromise be... View full abstract»

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  • A high-precision high-resolution WTA-MAX circuit of O(N) complexity

    Publication Year: 2002 , Page(s): 48 - 53
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (267 KB) |  | HTML iconHTML  

    The design and implementation of a high-precision, high-resolution winner-takes-all-maximum (WTA-MAX) circuit of O(N) complexity are presented. The proposed technique also allows straightforward implementation of loser-takes-all-minimum (LTA-MIN) circuit. To satisfy a given precision specification, conventional techniques rely on matching of an N-size transistor array, where N is the input count o... View full abstract»

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  • A cochlear filter implemented with a field-programmable gate array

    Publication Year: 2002 , Page(s): 54 - 60
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    A digital cochlear filter was designed and implemented in hardware using a Xilinx XC4010 field-programmable gate array (FPGA) chip. The filter gives a good fit to biological data. It is a tenth-order recursive filter implemented as a parallel combination of low-order elements. A systematic approach to the design problem enabled us to achieve a good fit to cochlear data with efficiency of hardware ... View full abstract»

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  • Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

    Publication Year: 2002 , Page(s): 25 - 30
    Cited by:  Papers (48)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones. We have done over 10,000 HSPICE simulation runs of all the different adders in different input patterns, frequencie... View full abstract»

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  • Design of squarers modulo A with low-level pipelining

    Publication Year: 2002 , Page(s): 31 - 41
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (414 KB) |  | HTML iconHTML  

    A squarer mod A is a circuit that computes the residue of the square of an integer X taken modulo a positive integer A. It is an essential building block in a variety of high-speed hardware for a digital signal processor (DSP) using the residue number system (RNS) which implements, e.g., the quarter-square modulo multiplication, the squared Euclidean distance, correlation, and circular convolution... View full abstract»

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  • The design of hybrid carry-lookahead/carry-select adders

    Publication Year: 2002 , Page(s): 16 - 24
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (340 KB) |  | HTML iconHTML  

    In this paper, we present a general architecture for designing hybrid carry-lookahead/carry-select adders. Several previous adders in the literature are all special cases of this general architecture. They differ in the way Boolean functions for the carries are implemented. Based on the general architecture, we propose a new implementation of high-speed 56-bit hybrid adder. The new adder directly ... View full abstract»

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  • Dynamic-range enhancement of an optimized 1-bit A/D converter

    Publication Year: 2002 , Page(s): 42 - 47
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (358 KB) |  | HTML iconHTML  

    A technique is demonstrated for extending the dynamic range of 1-bit analog-to-digital converters (ADCs) that sample at the maximum rate using a sinusoid reference r(t)=Ar cos(2πfrt). The ADC has a detection limit B=πAr δ/▵, where 2δs is the base-clock period, and ▵=sampling interval=1/2fr⩾2δ. Optimal samp... View full abstract»

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  • Stability of 2-D periodically shift variant filters

    Publication Year: 2002 , Page(s): 61 - 64
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (266 KB)  

    The stability of two-dimensional (2-D) periodically shift varying (PSV) filters is considered. The considered system is represented in state space by the first model of Fornasini-Marchesini (FM) with periodic coefficients. The stability of this model is then studied. Two necessary conditions and two sufficient conditions are established for asymptotic stability. The conditions are easy to use and ... View full abstract»

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  • Convergence rate analysis of fast predictor-based least squares algorithm

    Publication Year: 2002 , Page(s): 11 - 15
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (276 KB) |  | HTML iconHTML  

    The numerical stability and convergence rate properties of least mean square (LMS) and recursive least squares (RLS) algorithms have attracted much interest in the literature, however, very few investigations have been reported concerning the fast Newton transversal filter (FNTF) algorithm. The FNTF algorithm spans the range of adaptive algorithms from LMS to RLS and is, therefore, more flexible i... View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope