By Topic

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 11 • Date Nov 2000

Filter Results

Displaying Results 1 - 25 of 27
  • Design of nonuniform multirate filter banks by semidefinite programming

    Publication Year: 2000 , Page(s): 1311 - 1314
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    In this brief, the design of finite-impulse response (FIR) filter banks by semidefinite programming is discussed. The initial analysis filters are designed according to the characteristics of the input. By the design procedure, for the given set of analysis filters, synthesis filters are found so that the H norm of the error system is minimized over all synthesis filters that have a prespecified order. Then, the synthesis filters obtained in the previous step are fixed and the analysis filters are found similarly. By iteration, the H norm of the error system decreases until it converges to its final value. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Complex composite spectra of Unified Complex Hadamard transform for logic functions

    Publication Year: 2000 , Page(s): 1291 - 1297
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    A method to evaluate the Unified Complex Hadamard spectra of AND, OR, and XOR for Boolean functions, directly from the spectra of the functions, is presented. The results are given using a general coding scheme, and different possible codings of Boolean functions are also discussed. A new definition of the convolution operation called complex convolution is derived. Different properties of such a convolution are presented. A theorem giving final formulas for the composite Unified Complex Hadamard spectra of Boolean functions is stated in terms of the complex convolution. Efficient representations of the spectra in the form of decision diagrams are presented. An application of Unified Complex Hadamard Transform in image watermarking is also discussed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient design of integrated switched-capacitor decimation filters

    Publication Year: 2000 , Page(s): 1314 - 1318
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    The infinite-impulse response (IIR) switched-capacitor (SC) decimation filter scheme proposed in this brief is based on the polyphase decomposition of an Mth band IIR low-pass filter, and uses first- and second-order all-pass SC filters as basic building blocks, operating at the lower sampling rate, resulting in reduced power consumption, capacitance spread, and capacitance area. The SC realization has low sensitivity with respect to capacitance ratio errors, especially in the passband, due to the use of structurally all-pass filters. These properties have been verified by computer analysis. An illustrative design example is included, along with comparisons with other approaches reported in the literature. Laboratory results obtained with a prototype filter are shown, as well. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Approximating the universal active element

    Publication Year: 2000 , Page(s): 1160 - 1169
    Cited by:  Papers (45)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    The classification of universal amplifiers presented in this paper places all operational amplifiers and current conveyors known from the literature into a common framework, together with abstract concepts such as the universal active element and the or. Our approach is new in that we base it on four-terminal theory, which results in a classification that is more extensive but not more complex than classifications derived using two-port theory. It turns out that our classification contains a new type of operational amplifier, which we call current-feedback operational transconductance amplifier (CFB OTA), and also a new class of voltage-inverting current conveyors. We then demonstrate that our classification is very closely related to integrated-amplifier design by showing how all operational amplifiers and current conveyors can be implemented in CMOS using only a few CMOS circuits. Since the basic ideas behind CMOS and bipolar circuits are very similar, this paper is not process specific and can be seen as an attempt to bridge the gap between amplifier theory and amplifier design that has become ever wider in the past few years. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low Vt CMOS implementation of an LPLV digital filter core for portable audio applications

    Publication Year: 2000 , Page(s): 1297 - 1300
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (88 KB)  

    A low power 32nd-order digital filter for portable audio applications has been designed and implemented in a single threshold 1-V 0.5-μm CMOS process. The design is full custom, using a combination of conventional CMOS and pass-transistor circuits, optimized for low energy consumption and small area. The filter features up to 16 biquad sections with programmable coefficients and performs fixed-point computations with 16-bit resolution. The measured average energy consumption of 330 pJ per biquad computation indicates that the implementation of complex digital signal processing in a single-threshold low-voltage process is a viable alternative to implementations in multiple threshold processes. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A study of dynamic element-matching techniques for 3-level unit elements

    Publication Year: 2000 , Page(s): 1177 - 1187
    Cited by:  Papers (12)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    Highly linear 3-level unit elements are available in any fully differential circuit. This is because each unit element in such a circuit can be either positively selected, negatively selected, or not selected. This paper presents a study of dynamic element techniques for such elements. It is shown how traditional dynamic element-matching techniques for 2-level unit elements such as the data directed swapper, the vector selector and the tree structure can be adapted toward linear 3-level elements. In all these cases, the amount of hardware is reduced significantly by using 3-level elements. Also several efficient "data weighted averaging"-like implementations are presented. Then the effect of the nonlinearity of the 3-level unit element is analyzed. It is shown that this gives an additional error contribution that may limit the performance. Therefore, several efficient techniques to shape this effect as well are introduced. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pipelined CORDIC-based cascade orthogonal IIR digital filters

    Publication Year: 2000 , Page(s): 1238 - 1253
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    CORDIC-based cascade orthogonal infinite-impulse response (IIR) digital filters possess desirable properties for VLSI implementations such as local connection, regularity, absence of limit cycle and overflow oscillations, and good finite word-length behavior. However, the achievable sample rate of these filters is limited, since these structures cannot be pipelined at finer levels (such as bit or multi-bit level) due to the presence of feedback loops. In this paper, we present a novel approach to design pipelined CORDIC-based cascade orthogonal IIR digital filters using the transfer function approach. We first present a systematic way to synthesize cascade orthogonal IIR digital filters using scalar lossless inverse scattering theory, and realize the filter transfer function as a cascade inter-connection of orthogonal sections where each section implements one real zero or a pair of complex conjugate zeroes of the transfer function. In this way, the filter achieves low sensitivity over the entire filter spectrum. Novel pipelining techniques for both coarse-grain and fine-grain pipelining of these filters are then proposed. In coarse-grain pipelining, we present a novel method based on retiming and orthogonal matrix decomposition techniques which can increase the maximum filter sample rate to O(1) level which is independent of the filter order. In fine-grain pipelining, we present a novel method based on constraint filter design and polyphase decomposition techniques which could increase the maximum filter sample rate to any desired level. The proposed architecture for coarse-grain pipelining consists of only Givens rotations, and the one for fine-grain pipelining consists of only Givens rotations and a few additions. Both architectures can be realized using CORDIC arithmetic-based processors. Finally, finite word-length simulations are carried out to compare the performance of different topologies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pseudo-exponential function for MOSFETs in saturation

    Publication Year: 2000 , Page(s): 1318 - 1321
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    In this paper, according to the Taylor's series expansion, two pseudo-exponential circuits were realized. The proposed circuits provide a simple method to synthesize pseudo-exponential circuits. Both of the circuits were composed of MOS transistors operating in saturation. One of the pseudo-exponential function circuits is voltage-mode and was tested using discrete components. The other one is current-mode, which is verified with the 0.8 μm CMOS process by Hspice simulations. The results confirm the feasibility of the proposed circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An energy-efficient noise-tolerant dynamic circuit technique

    Publication Year: 2000 , Page(s): 1300 - 1306
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    Noise in deep submicron technology combined with the move toward dynamic circuit techniques have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. The average noise threshold energy (ANTE) and the energy normalized ANTE (NANTE) metrics are proposed to quantify the noise immunity and energy efficiency, respectively. Simulation results in 0.35-μm CMOS for NAND gate and full-adder designs indicate that the proposed technique improves the ANTE and NANTE by 2× and 1.4× over conventional domino circuits. The improvement in the NANTE is 11% higher than the existing noise-tolerance techniques. Furthermore, the proposed technique has a smaller area overhead (36%) as compared to static circuits whose area overhead is 60%. Also presented in this paper is an ASIC developed in 0.35-μm CMOS to evaluate the performance of the proposed technique. Experimental results demonstrate a 27% average improvement in noise immunity over conventional dynamic circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of low-cost and high-throughput linear arrays for DFT computations: algorithms, architectures, and implementations

    Publication Year: 2000 , Page(s): 1188 - 1203
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    Recursive algorithms for discrete Fourier transform (DFT) computation are proposed, where the common entries of the decomposed matrices are factored out in order to reduce the number of multipliers during implementation. The derived algorithms are essentially band-matrix-vector multiplications with matrix bandwidth of 3 in the radix-2 case and bandwidth of 7 in the radix-4 case. Low cost architectures are derived using an efficient mapping technique for the corresponding heterogeneous dependence graphs of the decomposed band matrices. Only log2 N(3 log4 N) adders and log2 N-1(log4 N-1) multipliers are needed to compute the DFT of size N using the proposed radix-2 (radix-4) linear array architectures, a great saving in hardware cost compared to previous approaches. Due to the simplicity and regularity of the architectures, it is possible to reduce the power consumption of the DFT processors by temporarily disabling the multiplier units at proper time steps. VLSI implementations of an 8-point radix-2 DFT processor and a 64-point radix-4 DFT processor are also given. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithm-based low-power/high-speed Reed-Solomon decoder design

    Publication Year: 2000 , Page(s): 1254 - 1270
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    With the spread of Reed-Solomon (RS) codes to portable wireless applications, low-power RS decoder design has become important. This paper discusses how the Berlekamp Massey decoding algorithm can be modified and mapped to obtain a low-power architecture. In addition, architecture level modifications that speed-up the syndrome and error computations are proposed. Then the VLSI architecture and design of the proposed low power/high-speed decoder is presented. The proposed design is compared with a normal design that does not use these algorithm/architecture modifications. The power reduction when compared to the normal design is estimated. The results indicate a power reduction of about 40% or a speed-up of 1.34. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Techniques for preventing tonal behavior of data weighted averaging algorithm in Σ-Δ modulators

    Publication Year: 2000 , Page(s): 1137 - 1144
    Cited by:  Papers (15)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    Two techniques for prevention of in-band tones in DWA mismatch noise shaping algorithm are presented. "offset technique" moves in-band tones away from baseband, improving SNR by ∼10 dB, and attenuates maximum in-band tone by as much as ∼25 dB. "Randomized DWA" is a combination of simultaneous randomization and DWA, which attenuates tonal behavior in all frequencies, preventing aliasing of tones or tone shifting for any arbitrary input signal. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Neural implementation of unconstrained minimum L1-norm optimization-least absolute deviation model and its application to time delay estimation

    Publication Year: 2000 , Page(s): 1214 - 1226
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    Least absolute deviation (LAD) optimization model, also called the unconstrained minimum L1-norm optimization model, has found extensive applications in linear parameter estimations. L1-norm model is superior to Lp-norm (p>1) models in non-Gaussian noise environments or even in chaos, especially for signals that contain sharp transitions (such as biomedical signals with spiky series or motion artifacts) or chaotic dynamic processes. However, its implementation is more difficult due to discontinuous derivatives, especially compared with the least-squares model (L2-norm). In this paper, neural implementation of LAD optimization model is presented, where a new neural network is constructed and its performance in LAD optimization is evaluated theoretically and experimentally. Then, the application of the proposed LAD neural network (LADNN) to time delay estimation (TDE) is presented. In TDE, a given signal is modeled using the moving average (MA) model. The MA parameters are estimated by using the LADNN and the time delay corresponds to the time index at which the MA coefficients have a peak. Compared with higher order spectra (HOS)-based TDE methods, the LADNN-based method is free of the assumption that the signal is non-Gaussian and the noises are Gaussian, which is closer to real situations. Experiments under three different noise environments, Gaussian, non-Gaussian and chaotic, are conducted to compare the proposed TDE method with the existing HOS-based method. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-swing MOS cascode bias circuit

    Publication Year: 2000 , Page(s): 1325 - 1328
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    In this paper, we propose a very simple bias circuit that allows for maximum output voltage swing of MOSFET cascode stages. The circuit topology is valid for any current density and is technology independent. Starting from the saturation voltage and from the current density of the cascode stage, we determine the aspect ratio of the transistors in the bias circuit in order to maximize the output voltage swing. Experimental results validate the strategy for designing the bias network. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Single-chip CMOS CCD camera interface based on digitally controlled capacitor-segment combination

    Publication Year: 2000 , Page(s): 1338 - 1343
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    This work describes a single-chip solution for CMOS charge-coupled device (CCD) camera interface systems. The required gain of the automatic gain control circuit (AGC) in the proposed system is controlled directly by digital bits without conventional extra digital-to-analog (D/A) converters, and the signal-settling behavior is almost independent of AGC gain variations at video speeds. A capacitor-segment combination technique to implement large capacitances considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A layout scheme minimizing truncation errors shows AGC matching accuracy better than 0.1%. Nonlinear errors such as offsets in signal paths are automatically measured during black-level correction. The outputs from the AGC are transferred to a 10 b analog-to-digital (A/D) converter integrated on the same chip. The prototype implemented in a 0.5 μm n-well CMOS process shows the 32 dB AGC dynamic range in 1/8-dB gain steps with 173 mW at 3 V and 25 MHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the use of periodic clock changes to implement linear periodic time-varying filters

    Publication Year: 2000 , Page(s): 1152 - 1159
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    A stationary process subjected to a linear periodic time-varying filter becomes cyclostationary. Under certain inversibility conditions, perfect linear reconstruction of a bandlimited input process can be obtained when the filter is known. In this paper, we show an original implementation method to realize a linear periodic filter by means of periodic clock changes (PCCs) that corresponds to a physical model and presents a low implementation cost. We also present how periodic clock changes can be implemented in practice. Moreover, we introduce a method to estimate the parameters of the obtained filter necessary for the reconstruction. This estimation is particularly useful when the signals are sampled. We apply these results to analog scrambling. Examples are given both for a continuous valued signal and a binary signal. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families

    Publication Year: 2000 , Page(s): 1279 - 1290
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    The delay fault testing in logic circuits is studied. It is shown that by detecting delayed time response in a transistor circuit, two types of faults are detected: (1) faults which cause delayed transitions at the output node due to some open defects and (2) faults which cause an intermediate voltage level at the output node. A test circuit is presented which enables the concurrent detection of delay faults. The proposed delay fault testing circuit does not substantially degrade the speed of the circuit under test (CUT). Simulation results show that this technique fits any design style. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sub-femtofarad capacitive sensing for microfabricated transducers using correlated double sampling and delta modulation

    Publication Year: 2000 , Page(s): 1170 - 1176
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    The theory, design, and measured performance of a circuit which measures very small capacitances, particularly suitable for microfabricated sensors relegated to a high parasitic environment, is presented. The circuit uses an existing capacitive sensing ASIC configured as a delta modulator to achieve a sense resolution of 0.53 fF at a 6-kHz sample rate in the presence of board-level parasitics. The applicability of the circuit to microfabricated sensors has been successfully demonstrated using a bulk-micromachined vertical transducer that is similar to many pressure sensors and accelerometers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance analysis of signed self-orthogonalizing adaptive lattice filter

    Publication Year: 2000 , Page(s): 1227 - 1237
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    This paper describes the novel signed self-orthogonalizing adaptive lattice filter (SSALF) structure to enhance the slow convergence rate caused by an eigenvalue disparity whilst constraining the level of the convergence rate and the misadjustment required by a specification. The SSALF structure is also implemented by the partial lattice predictor in order to reduce a computational complexity. The performance analysis based on the convergence model of the lattice predictor is given in terms of the mean-squared error and the variance of the reflection coefficient error. Computer simulations are undertaken to verify the performance and the applicability of the proposed filter structure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Discrete fractional Hilbert transform

    Publication Year: 2000 , Page(s): 1307 - 1311
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    The Hilbert transform plays an important role in the theory and practice of signal processing. A generalization of the Hilbert transform, the fractional Hilbert transform, was recently proposed, and it presents physical interpretation in the definition. In this paper, we develop the discrete fractional Hilbert transform, and apply the proposed discrete fractional Hilbert transform to the edge detection of digital images. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient modified-sinc filters for sigma-delta A/D converters

    Publication Year: 2000 , Page(s): 1204 - 1213
    Cited by:  Papers (50)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    In this paper, a method to design and implement a very efficient multistage decimation filter for a sigma-delta (ΣΔ) A/D converter is proposed. The scheme is composed of two stages, but the proposed method can be easily extended to a multiple-stage implementation. The first-stage filter is obtained by properly rotating the zero-pole distribution of a comb filter in the z-plane. The obtained structure exhibits linear phase and can be implemented by using a recursive structure with only two multipliers. The design phase is easy and very flexible. As most of the quantization noise is eliminated at the first stage, the second-stage filter can be designed with relaxed specifications. Any classical design algorithm can be used for it. An alternative scheme for the second stage can be obtained by splitting the stage into two substages, and the method proposed in this paper can be iterated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analog VLSI implementation of the Help If Needed Stereopsis Algorithm

    Publication Year: 2000 , Page(s): 1328 - 1337
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    This work introduces a novel clocked analog VLSI hardware system with an optical input that performs stereopsis. An algorithm called the Help If Needed Algorithm, developed previously, is readily mapped onto an analog VLSI platform. The system fits into the cellular neural network (CNN) paradigm. The circuit components that make up the cells of the CNN are designed with the constraint that they must function effectively and fit into the space available. In order to clarify the processing pathway, the system is described at the component and system levels. Each cell has an optical input, while the output is electrical. By utilizing an optical input, an analog VLSI silicon retina first stage can be connected to the stereopsis processor completely in parallel, creating a multi-stage artificial visual system. The physical system is composed of 2.0 μm Tinychips fabricated through MOSIS. Experimental data are presented that verify that the system performs as desired and successfully implements the Help If Needed Stereopsis Algorithm. The novel stereopsis processor is ideally suited for autonomous robots, or any application that requires a low power visual processing system. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Numerical device simulation of the composite triple-beat distortion of a cable television amplifier

    Publication Year: 2000 , Page(s): 1145 - 1151
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    The composite triple-beat (CTB) distortion of a cable television amplifier was simulated using numerical device simulation. The structures for the underlying bipolar transistors were created using numerical process simulation. Subsequent time-domain device simulation was performed in a mixed device-circuit mode for a 77-carrier input signal with a random phase relationship between carriers. Using a novel mathematical technique, the turn-on transient of the amplifier was subtracted from the periodic part of the output signal in order to reduce the simulation time required to resolve the CTB distortion. A Fourier transform mapped the resulting signal into the frequency domain, where the CTB distortion could be determined directly. This simulation methodology demonstrates the capability of correlating circuit level radio frequency figures of merit with the process conditions in a technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A switched-capacitor compatible membership function block

    Publication Year: 2000 , Page(s): 1321 - 1325
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    A new membership function block suitable for the switched capacitor (SC) technique is proposed. The circuit is based on an offset insensitive SC amplifier and presents triangular shape transcharacteristics. Thanks to the SC approach, good precision independent of process tolerances is achieved. The proposed implementation was realized in a 1.2-μm standard CMOS technology. Both simulation and experimental data showed good agreement between expected and measured values. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of an inner-product processor for hardware realization of multi-valued exponential bidirectional associative memory

    Publication Year: 2000 , Page(s): 1271 - 1278
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    Inner-product calculations are often required in digital neural computing. The critical path of the inner product of two vectors is the carry propagation delay generated from individual product terms. In this work, a novel and high-speed realization of an inner-product processor for the multi-valued exponential bidirectional associative memory (MV-eBAM) is presented in order to reduce the carry propagation delay, wherein the treatment of inner product of two vectors is given. Notably, a systolic-like architecture of digital compressors is used to reduce the carry propagation delay in the critical path of the inner product of two vectors. The architecture we propose here might offer a sub-optimal solution for the digital hardware realization of the inner-product computation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope