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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 11 • Date Nov. 1999

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Displaying Results 1 - 20 of 20
  • Corrections to "A comment on 'interstage gain proration technique for digital-domain multi-step adc calibration"

    Publication Year: 1999 , Page(s): 1
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  • Comments on "Chaotic digital encoding: an approach to secure communication" and reply

    Publication Year: 1999 , Page(s): 1445 - 1448
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (85 KB)  

    For original paper see ibid., vol. 40, no. 10, pp. 660-6 (1993). A proposal for using a chaotic system with finite wordlength as a means for encrypting data is criticized on the grounds that some of the proposed schemes are readily attacked in the "chosen plaintext" scenario. Moreover, the proposed schemes do not appear to have any advantages over more conventional cryptographic methods as far as security is concerned. View full abstract»

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  • Author's reply

    Publication Year: 1999 , Page(s): 1447 - 1448
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  • Comments on "Designing 1-V op-amps using standard digital CMOS technology

    Publication Year: 1999 , Page(s): 1448
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  • Comments on "Designing 1-V op-amps using standard digital CMOS technology" [and reply]

    Publication Year: 1999
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    In the above paper [see ibid., vol. 45, no. 7, p.769-80, 1998] the authors state that the concept of a so-called "bulk-driven" circuit is, in their opinion, original. However, this concept, called a "body-driven" circuit, was presented over ten years ago at the ECCTD'87 in Paris, France, and has been published in the proceedings of that conference. In 1991, another paper concerning this concept was published, in which the authors have cited our paper and have used the "body-driven" concept in the practical realization of a software-programmable CMOS telephone circuit. View full abstract»

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  • Corrections to "A comment on 'interstage gain proration technique for digital-domain multi-step adc calibration"

    Publication Year: 1999 , Page(s): 1449
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  • Fixed-point error analysis of two-channel perfect reconstruction filter banks with perfect alias cancellation

    Publication Year: 1999 , Page(s): 1437 - 1440
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    This paper studies the effects of fixed-point arithmetic in two-channel perfect reconstruction (PR) filter banks. Practical implementations of filter banks often require scaling of coefficients and differing binary word sizes to maintain dynamic range. When scaling is used with fixed precision arithmetic, the perfect alias cancellation (PAC) and PR constraints no longer hold. The main contribution of this paper is the derivation of constraints whereby PAC is maintained, even when coefficients are scaled and when the analysis and synthesis filter banks use different binary word lengths. Once PAC is established, the fixed-point effects on PR properties can be analyzed using standard methods. The theory is verified by comparing predicted and actual reconstruction signal-to-noise ratios resulting from simulating a symmetric wavelet transform View full abstract»

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  • Pipelined recursive digital filters: a general look-ahead scheme and optimal approximation

    Publication Year: 1999 , Page(s): 1415 - 1420
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    A new look-ahead (LA) scheme, distributed look-ahead (DLA), is proposed for pipelined implementation of recursive digital filters. It is established that, in the case of many recursive filters, DLA can provide equivalent and stable implementation with reduced multiplication and latch complexities, and higher area-efficiency. It also produces outputs with reduced delays, when compared with some existing LA schemes. Stability regions for the proposed scheme are also well defined. Next, a time-domain approximation method is proposed for direct design of pipelined recursive filters that can achieve superior match with reduced pipelined filter orders View full abstract»

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  • Considerations on applying OFDM in a highly efficient power amplifier

    Publication Year: 1999 , Page(s): 1329 - 1336
    Cited by:  Papers (19)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A major obstacle in applying orthogonal frequency-division multiplexing (OFDM) in wireless local networks is the need for a highly linear and efficient radio frequency power amplifier. The strong fluctuated envelope of an OFDM signal makes it difficult to build this kind of power amplifier. In this paper, we consider the use of the envelope elimination and restoration method for OFDM power amplification and evaluate its performance tradeoffs. The results are compared to the performance of a linear power amplifier with different power backoffs. In addition, as the envelope of an OFDM signal is concentrated at low level, the average output power is low when a low supply voltage power amplifier is used. Simulation is done to show that the signal power (or signal-to-noise ratio for fixed noise level) can be traded off with clipping level for optimum bit-error-rate without increasing power supply voltage View full abstract»

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  • An improved transmission-line model for MOS transistors

    Publication Year: 1999 , Page(s): 1380 - 1387
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    In this paper, we present a high-frequency small-signal model for MOSFET devices operating in the saturation regime. The model is based on a transmission-line treatment of the gate region, taking into account the distributed resistance-capacitance effects along the width of the device. The gate-source resistance, as well as the induced gate noise arising from the nonquasi-static operation, are included in the model. Closed-form solution of the noise and the y-parameters are obtained. The model is verified with measurements of an 0.8-μm device. The y-parameters model is in close agreement with the measured parameters up to 15 GHz, which is higher than the fT of the device. The noise model was also verified by comparing the modeled and measured noise resistance View full abstract»

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  • Noise figure and impedance matching in RF cascode amplifiers

    Publication Year: 1999 , Page(s): 1388 - 1396
    Cited by:  Papers (60)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    The noise figure in low-noise radio frequency cascode amplifiers using narrow-band input-impedance matching is exhaustively analyzed and accurate equations are derived which fit simulated results well. Moreover, the effect on noise performance of different impedance-matching approaches is discussed and fundamental limitations caused by specific matching networks are pointed out. Finally, an improved matching network is proposed which reduces dominant noise components, greatly improving noise figure. By using the same process parameters, calculations and simulations show that the proposed matching arrangement achieves a noise figure at 0.9 GHz, which is about 0.9-dB better than the state-of-the-art solution View full abstract»

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  • Frequency-estimation error variance of an adaptive scheme based on structured AR modeling

    Publication Year: 1999 , Page(s): 1361 - 1366
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    An on-line version of a recently proposed frequency-estimation algorithm based on structured autoregressive (AR) modeling of data is derived for the special case of a single cisoid in noise. The adaptive notch filter utilizes a weighted sum-of-squares of the AR prediction error that is recursively minimized with respect to the frequency of the cisoid. The steady-state performance of the algorithm is characterized by aid of a linear filter-approximation technique, and design rules for the tuning variables are given. An excellent agreement is demonstrated between the results predicted by theory and the measured performance based on numerical simulations. The tracking ability and noise rejection is compared both with the performance of alternative algorithms and with the appropriate Cramer-Rao bound. It is shown that the algorithm is close to being statistically efficient View full abstract»

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  • Exploring scalable schedules for IIR filters with resource constraints

    Publication Year: 1999 , Page(s): 1367 - 1379
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    Linear difference equations involving recurrences are fundamental equations that describe many important signal processes; in particular, infinite-duration impulse response (IIR) filters. Applying conventional dependence-preserving parallelization techniques such as software pipelining can only extract limited parallelism due to loop-carried dependences in the linear recurrences, and thus, cannot achieve scalable speedup given more resources. Furthermore, the previously published scheduling techniques did not address the tradeoffs between resource constraints and the processing speed of the resulting schedules, and thus, do not have the capability of exploring the design space of parallel schedules implementing IIR filters. In this paper, we present a novel approach, based on harmonic scheduling, that addresses the tradeoffs between resource constraints and the processing speed of the resulting schedules, which can be used to explore the design space of scalable parallel schedules implementing IIR filters with resource constraints. The salient features of our approach include a mathematical formulation of the relationship between the schedules, resource constraints and target performance, and capabilities for exploring design space in terms of those parameters. In particular, our approach can be used to successively approximate time-optimal schedules implementing IIR filters for a given target architecture. We illustrate our approach by giving an algorithm for deriving scalable schedules for IIR filters with a fixed number of identical multifunctional processors. As a further illustration, we derive rate-optimal schedules for IIR filters under more realistic constraints: using a fixed number of adders and multipliers and assuming that multiplication and addition take dissimilar execution times View full abstract»

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  • Unification of order-statistics based filters to piecewise-linear filters

    Publication Year: 1999 , Page(s): 1397 - 1403
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    Order-statistics based filters that were originally provided by the robust estimation theory have proved to be efficient in image/signal filtering in the presence of additive white noise or impulsive noise. Their algorithms are simple and easy to implement. Their analysis, however, is not straightforward. In this paper, we show that filters based on order statistics can be explained by using the theory of piecewise-linear (PWL) functions which was established originally for circuit analysis and has recently been applied to nonlinear filtering. We also prove that an L-filter is a PWL filter defined on IRn and a median filter by threshold decomposition is a piecewise-constant (PWC) filter on [0,M-1]n. The main results lead to the unification of order-statistics based filters with the PWL filter class. Based on the fact that PWL functions are a general class of approximation functions which are uniformly dense in the domain concerned, it is expected that the results obtained can provide a new way to the extension, as well as further study of, order-statistics based filters View full abstract»

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  • Design of stable IIR digital filters with equiripple passbands and peak-constrained least-squares stopbands

    Publication Year: 1999 , Page(s): 1421 - 1426
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    This paper describes an algorithmic development for the design of stable infinite impulse response (IIR) digital filters with equiripple passbands and peak-constrained least-squares stopbands. Central to the development is a re-formulation of the design problem as an iterative quadratic programming problem where the stability and equiripple passbands and peak-constrained requirements are met by imposing a system of linear inequality constraints while the LSS property is satisfied by minimizing a weighted least-squares type objective function View full abstract»

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  • Modified DFT filter banks with perfect reconstruction

    Publication Year: 1999 , Page(s): 1404 - 1414
    Cited by:  Papers (66)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    In this paper, essential features of the recently introduced modified discrete Fourier transform DFT (MDFT) filter bank are presented. First, it is shown that all analysis and synthesis filters-obtained by appropriate complex modulation of a low-pass prototype filter-are linear phase. This is important for subband image coding applications. Another important property is the structure-inherent alias cancellation: all odd alias spectra are automatically compensated in the synthesis filter bank. Further, the MDFT filter bank provides perfect reconstruction for the same prototypes as for cosine-modulated filter banks. Thus, the same design methods can be used. Finally, different mappings of the input signal into the subbands are discussed and a comparison to the well-known cosine-modulated filter banks is given View full abstract»

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  • 2D video rate SC FIR filters based on analog RAMs

    Publication Year: 1999 , Page(s): 1348 - 1360
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    Monolithic CMOS analog implementations of video systems are extremely attractive because of their low area and power requirements. Switched-capacitor circuits may advantageously replace many current digital solutions of video systems. However, special care must be used in order to handle, with standard CMOS technology, the problems related to the broadband characteristics of video systems. Moreover, two-dimensional (2D) filters require long delay lines, which are not easily implementable in the analog domain. Therefore, new design solutions must be developed, such as the architecture based on analog random-access memories for 2D video-rate switched-capacitor finite-impulse response (FIR) filters, proposed in this work. This structure can be optimized with respect to area requirements and precision requirements, because it allows the exploiting of impulse-response symmetries of linear-phase FIR fitters. The characteristics and the feasibility of the proposed design solution are demonstrated in the design of a 2D low-pass filter for picture-in-picture resizing View full abstract»

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  • Neuromorphic analog VLSI sensor for visual tracking: circuits and application examples

    Publication Year: 1999 , Page(s): 1337 - 1347
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    This paper presents a one-dimensional visual sensor, implemented on a single VLSI chip using analog neuromorphic circuits, for selectively detecting and tracking the position of the feature with the highest spatial contrast present in the visual scene. The chip's photoreceptors adapt to stationary backgrounds and can be tuned to respond maximally to specific target velocities. The sensor drastically reduces the amount of data to be transmitted to further processing stages by encoding, in real time, the position of the target in the form of a single continuous-time analog variable. We describe the circuits implementing the sensor and show applications to three examples of tracking tasks: a stand-alone visual tracking system, an active fully analog tracking system, and a mobile platform line-following system View full abstract»

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  • Analysis of ground-bounce induced substrate noise coupling in a low resistive bulk epitaxial process: design strategies to minimize noise effects on a mixed-signal chip

    Publication Year: 1999 , Page(s): 1427 - 1436
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    The industry trend toward system-on-chip solutions continues to push the limits of mixed-signal design. Increasing the integration of analog and digital circuitry causes a struggle to maintain analog signal integrity. Digital switching of noise coupling through the common substrate is both difficult to measure and difficult to control. This paper introduces and applies a practical first-order simulation methodology for performing a substrate noise analysis in a low resistive bulk process. Although this subject has been analyzed in numerous journal articles, few have applied their analysis method to a whole-chip design. This SPICE model will allow mixed-signal designers to determine design variables that will minimize substrate noise. This work elaborates on key aspects of substrate noise that available references do not handle adequately, including: sources of substrate noise, determination of power-rail and bulk-resonance frequencies, and alternatives for bulk biasing. The new model is used to analyze Motorola's 56824, the latest low-cost 16-bit digital signal processor design. The analysis includes the determination of: (1) the on-chip bus and I/O bus noise coupled to the substrate; (2) the dominant resonant frequencies in the chip; and (3) the best bulk-biasing alternative View full abstract»

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  • On the properties of the reduction-by-composition LMS algorithm

    Publication Year: 1999 , Page(s): 1440 - 1445
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    The recently proposed low-complexity reduction-by-composition least-mean-square (LMS) algorithm (RCLMS) costs only half the multiplications compared to that of the conventional direct-form LMS algorithm (DLMS). This work intends to characterize its properties and conditions for mean and mean-square convergence. Closed-form mean-square error (MSE) as a function of the LMS step-size μ and an extra compensation step-size α are derived, which are slightly larger than that of the DLMS algorithm. It is shown, when μ is small enough and α is properly chosen, the RCLMS algorithm has comparable performance to that of the DLMS algorithm. Simple working rules and ranges for α and μ to make such comparability are provided. For the algorithm to converge, a tight bound for α is also derived. The derived properties and conditions are verified by simulations View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope