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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 9 • Date Sept. 1999

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Displaying Results 1 - 17 of 17
  • Comments on "An arithmetic free parallel mixed-radix conversion algorithm"

    Publication Year: 1999 , Page(s): 1259 - 1260
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (58 KB)  

    For original paper see D.F. Miller and W.S. McCormick, ibid., vol.45, pp.158-62 (Jan. 1998). In the above paper, two algorithms based on look-up tables for mixed-radix conversion are presented. Here, we show that one of the algorithms had been previously published in 1978, and we also take this opportunity to speak of the use of look-up tables for the residue number system with present and future technologies. View full abstract»

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  • A new discrete fractional Fourier transform based on constrained eigendecomposition of DFT matrix by Lagrange multiplier method

    Publication Year: 1999 , Page(s): 1240 - 1245
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    This paper is concerned with the definition of the discrete fractional Fourier transform (DFRFT). First, an eigendecomposition of the discrete Fourier transform (DFT) matrix is derived by sampling the Hermite Gauss functions, which are eigenfunctions of the continuous Fourier transform and by performing a novel error-removal procedure. Then, the result of the eigendecomposition of the DFT matrix is used to define a new DFRFT. Finally, several numerical examples are illustrated to demonstrate that the proposed DFRFT is a better approximation to the continuous fractional Fourier transform than the conventional defined DFRFT View full abstract»

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  • A design technique for 2-D linear-phase frequency-sampling filters with fourfold symmetry

    Publication Year: 1999 , Page(s): 1253 - 1259
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    A two-dimensional (2-D) frequency-sampling filter approximates a desired frequency response by interpolating a frequency response through set frequency samples which are samples taken from the filter's frequency response. In this brief, a technique for designing 2-D Type 1-1, Type 1-2, Type 2-1, and Type 2-2 frequency-sampling filters that have real impulse responses, linear phase, and fourfold symmetry is developed that controls interpolation errors and approximates a desired frequency response by minimizing a weighted mean-square error over the passbands and stopbands subject to constraints on the filter's amplitude response View full abstract»

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  • Stochastic resonance in electrical circuits. II. Nonconventional stochastic resonance

    Publication Year: 1999 , Page(s): 1215 - 1224
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    For pt.I see ibid., vol.46, no.9, pp.1205-14 (1999). Stochastic resonance (SR), in which a periodic signal in a nonlinear system can be amplified by added noise, is discussed. The application of circuit modeling techniques to the conventional form of SR, which occurs in static bistable potentials, was considered in a companion paper. Here, the investigation of nonconventional forms of SR in part using similar electronic techniques is described. In the small-signal limit, the results are well described in terms of linear response theory. Some other phenomena of topical interest, closely related to SR, are also treated View full abstract»

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  • Multiplierless and hierarchical structures for maximally flat half-band FIR filters

    Publication Year: 1999 , Page(s): 1225 - 1230
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    A simple method to derive a closed-form expression for the transfer function of linear-phase half-band filters with maximally flat amplitude-response characteristics is presented. The method is based on the binomial series. It results in hierarchical and modular structures with low hardware complexity for low-pass and high-pass filters. For a filter of a given order, the structures provide access to ail maximally flat filters of lower orders. Two types of structures are presented. The first enjoys a set of multiplier coefficients with reduced dynamic range, and the second can be realized free of multiplier coefficients in a modular manner. Extension of the order of the filter can be achieved by cascading additional building blocks for the former structure or by adding an extra layer of modules for the latter structure. The proposed structures and formulas are applicable to maximally flat Hilbert transformers as well View full abstract»

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  • N-path and pseudo-N-path cells for switched-current signal processing

    Publication Year: 1999 , Page(s): 1148 - 1160
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    Novel switched-current N-path and pseudo-N-path cells are proposed, which allow the transformation of a z-domain low-pass reference filter into a bandpass one. The three types of cells, a forward Euler, backward Euler, and bilinear integrator, perform the z→-z and z→-zN transformations, which avoid clock-feedthrough noise in the realized filter passband. The pseudo-N-path cells operate on the circulating-delay principle, which avoids mirror-frequency noise due to path mismatches and require only standard biphase clocks to operate. The effects of circuit nonidealities are studied and performance comparisons are made with a conventional narrow-band bandpass filter. The robust frequency stability characteristic makes the cells suitable for narrow-band bandpass applications. Results of an HSPICE simulation example is given for a sixth-order pseudo-N-path filter View full abstract»

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  • Hardware implementation of a visual-motion pixel using oriented spatiotemporal neural filters

    Publication Year: 1999 , Page(s): 1121 - 1136
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    A pixel for measuring two-dimensional (2-D) visual motion with two one-dimensional (1-D) detectors has been implemented in very large scale integration. Based on the spatiotemporal feature extraction model of Adelson and Bergen, the pixel is realized using a general-purpose analog neural computer and a silicon retina. Because the neural computer only offers sum-and-threshold neurons, the Adelson and Bergen's model is modified. The quadratic nonlinearity is replaced with a full-wave rectification, while the contrast normalization is replaced with edge detection and thresholding. Motion is extracted in two dimensions by using two 1-D detectors with spatial smoothing orthogonal to the direction of motion. Analysis shows that our pixel, although it has some limitations, has much lower hardware complexity compared to the full 2-D model. It also produces more accurate results and has a reduced aperture problem compared to the two 1-D model with no smoothing. Real-time velocity is represented as a distribution of activity of the 18 X and 18 Y velocity-tuned neural filters View full abstract»

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  • A fast-search motion estimation method and its VLSI architecture

    Publication Year: 1999 , Page(s): 1233 - 1240
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    An efficient search algorithm for block motion estimation is proposed in this paper. By using fuzzy reasoning, the algorithm can determine the motion vectors of image blocks quickly and correctly. Our experimental results show that the proposed algorithm performs better than other search algorithms, such as 3SS, CS, PHODS, 4SS, BBGDS, SES, PSA, and GPS. The VLSI architecture of the algorithm has been developed, and in simulation it yields a search rate of 683 000 blocks/s with a clock rate of 66 MHz View full abstract»

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  • An integrated high-frequency narrow-band high-resolution synthesizer

    Publication Year: 1999 , Page(s): 1171 - 1178
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    A frequency synthesizer employing a new digital-frequency measurement method in a feedback loop is described. The synthesizer features high-frequency resolution and a high operating frequency. The mostly digital nature of the synthesizer and relaxed voltage-controlled oscillator requirements also make the synthesizer suitable for integration. Models for the synthesizer are developed and experimental results from a prototype are given View full abstract»

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  • Design of ADPLL for both large lock-in range and good tracking performance

    Publication Year: 1999 , Page(s): 1192 - 1204
    Cited by:  Papers (6)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    This paper describes a new all-digital phase locked loop (ADPLL). The proposed ADPLL contains a frequency offset estimator and a phase-error estimator. Thereby, it can provide both large lock-in range and good tracking performance. Furthermore, it does not suffer severely from the phase jitter due to the quantization effect of the numerically controlled oscillator. In addition to some mathematical performance analysis, various simulation and experimental results are also presented to illuminate further the practical use and the excellent performance of the proposed ADPLL View full abstract»

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  • Multiple input/multiple output linear prediction of subband signals

    Publication Year: 1999 , Page(s): 1230 - 1233
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    The prediction of subband signals usually incurs a penalty, compared to the prediction of the fullband signal. This problem can be solved by exploiting the statistical dependencies between subbands with multiple input/multiple output (MIMO) linear prediction tools. We derive the MMO linear predictor for a minimum mean-squared error criterion. The interest of adaptive structures is briefly discussed. It is shown next how these tools can be applied to waveform coding. Finally, the performance of the proposed methods is numerically evaluated and tested on a real-world image signal View full abstract»

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  • Stochastic resonance in electrical circuits. I. Conventional stochastic resonance

    Publication Year: 1999 , Page(s): 1205 - 1214
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    Stochastic resonance (SR), a phenomenon in which a periodic signal in a nonlinear system can be amplified by added noise, is introduced and discussed. Techniques for investigating SR using electronic circuits are described in practical terms. The physical nature of SR, and the explanation of weak-noise SR as a linear response phenomenon, are considered. Conventional SR, for systems characterized by static bistable potentials, is described together with examples of the data obtainable from the circuit models used to test the theory View full abstract»

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  • A new register allocation scheme for low-power data format converters

    Publication Year: 1999 , Page(s): 1250 - 1253
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    In many applications, such as digital signal processing, data format converters (DFC) are used to reformat the data transferred between processing modules. Various methods have been proposed to synthesize DFC architectures while optimizing the number of registers used to store the data. In this brief, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the DFC. Low-power DFC's are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over precious techniques View full abstract»

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  • Improved structures for programmable filters: application in a switched-capacitor adaptive filter design

    Publication Year: 1999 , Page(s): 1137 - 1147
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    In designing switched-capacitor (SC) filters for high-frequency operation, there is a tradeoff to be made between the gain and the speed of the operational amplifiers (op amps). Taking into account this fact, we present in this paper new structures (an SC integrator and an SC gain stage) which relax the constraint requirements on the op amp while achieving improved performance accuracy. These structures use the double-sampled technique, which increases by a factor of two the maximum speed of operation and correctly operate even with low dc-gain op amps. In order to effectively use all features (low sensitivity to op-amp imperfections) of these SC building blocks in the implementation of an adaptive filter, we also describe an offset-cancelled tunable SC gain stage based on four-quadrant analog multiplier cells. Numerical results are reported to confirm the viability of the proposed design method, and techniques to further improve the adaptive filter electrical characteristics are discussed View full abstract»

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  • An adiabatic differential logic for low-power digital systems

    Publication Year: 1999 , Page(s): 1245 - 1250
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    A new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL) is presented. ADCPL is a dual-rail logic with refatively low gate complexity. It operates from a two-phase nonoverlapping supply clock, power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed, Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50%-70% can be achieved over the static complimentary metal oxide semiconductor case within a practical operation frequency range. The results also show that the lower the operating frequency, the larger the energy savings for an ADCPL circuit View full abstract»

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  • Discrete Lagrangian methods for optimizing the design of multiplierless QMF banks

    Publication Year: 1999 , Page(s): 1179 - 1191
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    In this paper, we present a new discrete Lagrangian method for designing multiplierless quadrature mirror filter banks. The filter coefficients in these filter banks are in powers-of-two, where numbers are represented as sums or differences of powers of two (also called canonical signed digit representation), and multiplications are carried out as additions, subtractions, and shifts. We formulate the design problem as a nonlinear discrete constrained optimization problem, using reconstruction error as the objective, and stopband and passband energies, stopband and passband ripples, and transition bandwidth as constraints. Using the performance of the best existing designs as constraints, we search for designs that improve over the best existing designs with respect to all the performance metrics. We propose a new discrete Lagrangian method for finding good designs and study methods to improve the convergence speed of Lagrangian methods without affecting their solution quality. This is done by adjusting dynamically the relative weights between the objective and the Lagrangian part. We show that our method can find designs that improve over Johnston's benchmark designs using a maximum of three to six ONE bits in each filter coefficient instead of using floating-point representations. Our approach is general and is applicable to the design of other types of multiplierless filter banks View full abstract»

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  • Ladder derived switched-current decimators and interpolators

    Publication Year: 1999 , Page(s): 1161 - 1170
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    Switched-current elliptic decimators and interpolators based on bilinear-transformed low-sensitivity ladder structures are proposed. The combination of polyphase networks and doubly terminated ladder structures preserve low passband sensitivity and maximizes time for settling by operating at the lower sampling frequency. The decimators are derived via a z-domain multirate transformation procedure. Two different types of decimator architectures, finite-impulse response (FIR)-infinite-impulse response (IIR) cascade (FIC) and multiple feed-in (MFI) are presented and compared. The complementary IIR-FIR cascade (IFC) and multiple feed-out (MFO) interpolator structures are obtained by direct transposition, which avoids the need for redesign. A third-order elliptic low pass filter is used as prototype for deriving the decimators and interpolators. The circuits are verified by SCNAP4 and HSPICE simulations View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope