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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 7 • Date July 1999

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Displaying Results 1 - 20 of 20
  • Guest editorial introduction to the special issue on ISCAS'98

    Publication Year: 1999 , Page(s): 849 - 851
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    Freely Available from IEEE
  • The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

    Publication Year: 1999 , Page(s): 941 - 945
    Cited by:  Papers (36)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    This brief proposes a new- architecture for the oversampling delta-sigma analog-to-digital converter (ADC) utilizing a voltage controlled oscillator (VCO). The VCO, associated with a pulse counter, works as a high-speed quantizer. This VCO quantizer also has the function of first-order noise shaping because the phase of the output pulse is an integrated quantity of the input voltage. If the maximum VCO frequency (fvm) is designed in the range of (2bq-2)fos<fvm< (2bq-1) fos and a bq-bit counter is used, a multibit (bq-bit) quantizer can be realized, where fos is the oversampling frequency. The performance of the proposed converter is evaluated using a functional simulation. A 59-dB SNR at a 5-MHz bandwidth is obtained with fos=400 MHz, even in the case of a 1-bit quantizer. The multibit quantizer using a high frequency VCO significantly improves an SNR and signal bandwidth. This architecture is highly suitable for implementation with deep sub-μm CMOS devices, which can attain improved switching speeds and reduce power dissipation during low voltage operation. It provides wideband oversampling ADC for video and wireless signals and a low voltage system-on-a-chip solution for multimedia applications View full abstract»

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  • Adaptation in a VLSI model of a neuron

    Publication Year: 1999 , Page(s): 967 - 970
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    We have designed, fabricated, and tested an analog very large-scale integrated (VLSI) circuit model of a biological neuron that implements self-adaptation of its parameters. We show that the addition of this self-adaptation to our model neuron can facilitate: (1) single parameter control over a multiparameter system; (2) stability of the system to fluctuations in parameters; and (3) coordinated modulation of parameters to achieve a desired behavior View full abstract»

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  • Real-time streaming video with adaptive bandwidth control and DCT-based error concealment

    Publication Year: 1999 , Page(s): 951 - 956
    Cited by:  Papers (8)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    This work deals with dropped streaming video packets from the viewpoint of minimizing future dropped packets, as well as restoring data lost in packets already dropped, specifically geared toward real-time transmission of H.263+ bitstream. Minimization of future dropped packets is achieved by an adaptive least mean squares bandwidth (BW) controller predicting the available bandwidth supported by the Internet with relatively little loss. Restoration of lost video data is performed by a combination of error concealment (EC) techniques, including interpolation of border pixels in DCT domain. All algorithms presented are computationally inexpensive and thus suited for real-time video applications View full abstract»

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  • Single-chip CMOS image sensors for a retina implant system

    Publication Year: 1999 , Page(s): 870 - 877
    Cited by:  Papers (27)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1536 KB)  

    This work describes the architecture and realization of microelectronic components for a retina-implant system that will provide visual sensations to patients suffering from photoreceptor degeneration. Special circuitry has been developed for a fast single-chip CMOS image sensor system, which provides high dynamic range of more than seven decades (without any electronic or mechanical shutter) corresponding to the performance of the human eye. This image sensor system is directly coupled to a digital filter and a signal processor that compute the so-called receptive-field function for generation of the stimulation data. These external components are wireless, linked to an implanted flexible silicon multielectrode stimulator, which generates electrical signals for electrostimulation of the intact ganglion cells. All components, including additional hardware for digital signal processing and wireless data and power transmission, have been fabricated using in-house standard CMOS technology View full abstract»

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  • Blind joint equalization and multiuser detection for DS-CDMA in unknown correlated noise

    Publication Year: 1999 , Page(s): 886 - 895
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    The problem of blind demodulation of multiuser information symbols in an asynchronous multipath CDMA network in the presence of multiple-access interference (MAI), intersymbol interference (ISI), and ambient channel noise is considered. First, a discrete-time signal model for a multipath code-division multiple-access channel is developed, based upon which several linear receiver structures are defined. Blind channel-estimation methods exploiting the orthogonality between the signal and noise subspaces are then discussed. In particular, channel estimation in the presence of unknown correlated noise is considered. It is assumed that the receiver employs two well-separated antennas, such that the noise is spatially uncorrelated. Two subspace methods for estimating the channel response are examined, based on, respectively, the singular value decomposition (SVD) and the canonical correlation decomposition (CCD) of the cross-correlation matrix of the signals received by the two antennas. Simulation results show that the CCD-based method substantially outperforms the SVD-based method View full abstract»

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  • A CMOS optical preamplifier for wireless infrared communications

    Publication Year: 1999 , Page(s): 852 - 859
    Cited by:  Papers (41)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    This paper describes a CMOS optical preamplifier suitable for infrared wireless data communications. The preamplifier consists of a differential CMOS variable-gain transimpedance amplifier embedded in a larger feedback loop used to reject photocurrents generated by ambient light. Fabricated in a commercial 0.35-μm CMOS process, the preamplifier consumes 8 mW at 3 V, and provides 70 MHz bandwidth over a 77-dB dynamic range with a maximum transimpedance gain of 19 kΩ. The bandwidth is controlled within a factor of two over a 31-dB variation in gain View full abstract»

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  • RF low-noise amplifiers in BiCMOS technologies

    Publication Year: 1999 , Page(s): 974 - 977
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    This paper deals with the design of low-noise amplifiers (LNA) fabricated in BiCMOS technologies. The LNA's are based on an active inductor, which makes the topologies less sensitive to temperature variations and reduces the effects of process parameter tolerances. Experimental results show a 10-dB voltage gain at 1 GHz and unity-gain frequencies of 3.6 GHz. The noise figure, measured at 1 GHz, is 3.4 dB. The preamplifier has been fabricated using a 10-GHz BiCMOS technology View full abstract»

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  • On the design of the target-signal filter in adaptive beamforming

    Publication Year: 1999 , Page(s): 963 - 966
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    This brief deals with the improvement of jammer suppression for adaptive broadband beamforming. The analysis is carried out with a two-microphone Griffiths-Jim beamformer and a single jammer signal. By examining the derived optimal filter, a design strategy for the constant target-signal filter in the main channel of the adaptive beamformer is given. This leads to a substantial reduction in the required filter length of the adaptive filter, while maintaining the same jammer suppression. Furthermore, a faster rate of convergence can be achieved, as there are fewer filter coefficients that have to be adapted. The brief concludes with measurement results from a real-time implementation of an adaptive beamformer, showing that the proposed design method is effective, even when more than two microphones are used View full abstract»

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  • Bifurcation of switched nonlinear dynamical systems

    Publication Year: 1999 , Page(s): 878 - 885
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    This paper proposes a method to trace bifurcation sets for a piecewise-defined differential equation. In this system, the trajectory is continuous, but it is not differentiable at break points of the characteristics. We define the Poincare mapping by suitable local sections and local mappings, and thereby it is possible to calculate bifurcation parameter values. As an illustrated example, we analyze the behavior of a two-dimensional nonlinear autonomous system whose state space is constrained on two half planes concerned with state dependent switching characteristics. From investigation of bifurcation diagrams, we conclude that the tangent and global bifurcations play an important role for generating various periodic solutions and chaos. Some theoretical results are confirmed by laboratory experiments View full abstract»

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  • Design of very low-sensitivity and low-noise recursive filters using a cascade of low order lattice wave digital filters

    Publication Year: 1999 , Page(s): 906 - 914
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    Among the best structures for implementing recursive digital filters are lattice wave digital (LWD) filters (parallel connections of two all-pass filters). They are characterized by many attractive properties, such as a reasonably low coefficient sensitivity, a low roundoff noise level, and the absence of parasitic oscillations. The main drawback is that if the stopband attenuation is very high, then many bits are required for the coefficient representations. In order to get around this problem, a structure consisting of a cascade of LWD filters is introduced in this paper. The main advantage of the proposed structure, compared with the direct LWD filter, is that the poles of the new structure are further away from the unit circle. Consequently, the number of bits required for both the data and coefficient representations are significantly reduced. The price paid for these reductions is a slight increase in the overall filter order. By properly selecting the number of LWD filters and their orders and optimizing them, their coefficients are implementable by using a few powers of two. Filters of this kind are very attractive in very large-scale integration (VLSI) implementations, where a general multiplier is very costly View full abstract»

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  • A systematic technique for designing approximately linear phase recursive digital filters

    Publication Year: 1999 , Page(s): 956 - 963
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    A systematic method is introduced for designing approximately linear phase low-pass recursive digital filters. The filter structures under consideration are the conventional cascade form realization and the parallel connection of two allpass filters (lattice wave digital filters). Given the amplitude specifications, the filter parameters as well as the slope of the linear phase response are optimized in such a way that the maximum phase deviation from this linear phase is minimized in the passband. The filters are designed such that either the maximum amplitude value in the transition hand is less than or equal to the passband maximum or the amplitude response is monotonically decreasing in this band. The design scheme consists of two basic steps. The first step involves finding, in a simpler manner, a good suboptimum filter. In the second step, this filter is then used as an initial filter for further optimization that is carried out by the second algorithm of Dutta and Vidyasagar. Several examples are included illustrating the efficiency of the proposed design scheme. They also show the superiority of the resulting recursive filters over their linear phase finite-impulse response equivalents, especially in narrow-band cases View full abstract»

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  • Analytical expressions for harmonic distortion at low frequencies due to device mismatch in CMOS current mirrors

    Publication Year: 1999 , Page(s): 937 - 941
    Cited by:  Papers (13)
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    One of the origins of harmonic distortion in current mirrors is the inevitable mismatch between the mirror transistors. In this brief, we examine both single current mirrors and complementary class-AB current mirrors, and develop analytical expressions for the mismatch-induced harmonic distortion. The expressions are verified through simulations and are used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. The distortion model is combined with well-known statistical models for the device mismatch in order to establish a relation between geometrical parameters, distortion, and production yield. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors, but ultra-low distortion is not achievable, View full abstract»

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  • The formulation and implementation of an analog/digital control system for a 100-kW dc-to-dc buck chopper

    Publication Year: 1999 , Page(s): 971 - 974
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    The authors present a description of the design and implementation of an analog-to-digital controller for a 100-kW Ship Service Converter Module that is being used in a U.S. Navy reduced-scale dc zonal electric distribution system. The system requirements, control law, controller modes of operation and validation studies are documented View full abstract»

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  • Ultra low-voltage/low-power digital floating-gate circuits

    Publication Year: 1999 , Page(s): 930 - 936
    Cited by:  Papers (57)
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    This paper describes a novel technique for implementing ultra low-voltage/low-power digital circuits. The effective threshold voltage seen from a control gate is adjusted during a UV-light-activated tuning procedure. The optimal effective threshold voltage matching the supply voltage and speed may be programmed by UV light through an activated conductance between the power rails and the floating gates. Measured results are provided for gates operating down to 0.4-V power supply, using a standard double-poly CMOS process View full abstract»

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  • Voice extraction by on-line signal separation and recovery

    Publication Year: 1999 , Page(s): 915 - 922
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    The paper presents a formulation and an implementation of a system for voice output extraction (VOX) in real-time and near-real-time realistic real-world applications. A key component includes voice-signal separation and recovery from a mixture in practical environments. The signal separation and extraction component includes several algorithmic modules with a variety of sophistication levels, which include dynamic processing neural networks in tandem with (dynamic) adaptive methods. These adaptive methods make use of optimization theory subject to the dynamic network constraints to enable practical algorithms. The underlying technology platforms used in the compiled VOX software can significantly facilitate the embedding of speech recognition into many environments. Two demonstrations are described: one is PC-based and is near-real-time, the second is digital signal processing based and is real time. Sample results are described to quantify the performance of the overall systems View full abstract»

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  • The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock

    Publication Year: 1999 , Page(s): 945 - 950
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    The cores of the all-digital phase-locked loop (ADPLL) are the switch-tuning digital control oscillator (DCO) and the architecture, In this brief, we propose a DCO with reduced hardware cost, and architecture with characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high-performance microprocessors. The prototype of a 3.3-V ADPLL chip has been designed by TSMC's 0.6 μm SPDM CMOS process. The simulation shows that this ADPLL can operate in the range between 60 and 400 MHz, and at four times the reference clock frequency. The phase-lock process takes 47 clock cycles, and the phase error is less than 0.1 ns View full abstract»

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  • Distortion compensation in log-domain filters using state-space techniques

    Publication Year: 1999 , Page(s): 860 - 869
    Cited by:  Papers (4)
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    A new state-space method is proposed for the synthesis of “quasilog-domain” filters where the parasitic emitter resistance of transistors is built into the equation formulation. The explicit exponential maps for log domain filters are replaced with implicit exponential maps yielding nodal equations for active filters. The theory, which unifies a class of externally linear filters including log domain filters as a subset, is shown to be applicable to general higher order filters. Circuit realization is discussed, some example circuit topologies are proposed, and simulation results are offered to show the potential of the approach in improving log-domain filter performance View full abstract»

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  • Filter structures composed of all-pass and FIR filters for interpolation and decimation by a factor of two

    Publication Year: 1999 , Page(s): 896 - 905
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    This paper introduces filter structures for interpolation and decimation by a factor of two. The structures are derived by using the frequency-response masking approach, in which the overall filter makes use of a periodic model filter, its complementary filter, and two masking filters. The periodic model filters are obtained by replacing each delay element in a model filter with M delay elements in cascade. The model filter is a half-band infinite-impulse response (IIR) filter composed of two all-pass filters in parallel, whereas the masking filters are linear-phase finite-impulse response (FIR) filters. In the final interpolator and decimator structures the filtering takes plate at the lowest of the two sampling rates involved. The corresponding overall filter can be designed by separately optimizing a half-band IIR filter and a linear-phase FIR filter. Both nonlinear-phase and approximately linear-phase filters are considered. One advantage of the proposed filter structures over conventional half-band IIR filter structures is that their maximal sample frequency is M times higher, which may be utilized to increase the speed in an implementation and/or to reduce the power consumption via power supply voltage scaling techniques. In the case of approximately linear-phase filters, the computational complexity can be reduced as well. Several design examples are included demonstrating the properties and advantages of the proposed filter structures View full abstract»

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  • Signal coding for low power: fundamental limits and practical realizations

    Publication Year: 1999 , Page(s): 923 - 929
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    Transitions on high capacitance buses result in considerable system power dissipation. Therefore, various coding schemes have been proposed in the literature to encode the input signal in order to reduce the number of transitions. In this paper, we present: 1) fundamental bounds on the activity-reduction capability of any encoding scheme for a given source and 2) practical novel encoding schemes that approach these bounds. The fundamental bounds in 1) are obtained via an information theoretic approach, where a signal x(n) with entropy rate ℋ is coded with R bits per sample on average. The encoding schemes in 2) are developed via a communication-theoretic approach, whereby a data source is passed through a decorrelating function followed by a variant of entropy coding function which reduces the transition activity. Simulation results with an encoding scheme for data busses indicate an average reduction in transition activity of 36% View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope