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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 5 • Date May 1999

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Displaying Results 1 - 24 of 24
  • Comments on "Multifunction biquadratic filters using current conveyors"

    Publication Year: 1999 , Page(s): 658 - 659
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    Most of the authors accept that a current conveyor-based filter or oscillator will exhibit low output impedance, permitting easy cascadability, and no buffering needed if the output is taken from the x terminal of the CCII, as is also claimed by the above paper [see ibid., vol. 44, p. 956-8,1997]. The aim of this comment is to show that such a direct conclusion is not possible. The generally accepted behavior of the x terminal is that it is a low-impedance voltage source since it copies the voltage at the y terminal. However, it may be shown that there are cases where the x terminal alone acts as a current source with high output impedance. Conversely, a circuit where the output is taken from a node with only y and z terminals connected, the node may exhibit low output impedance. In this comment, both cases are illustrated by simple theory and examples. View full abstract»

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  • Corrections to "CMOS transconductance multipliers: a tutorial"

    Publication Year: 1999 , Page(s): 660
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6 KB)  

    First Page of the Article
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  • Design and analysis of high performance current reference generators for low-power CMOS data converters

    Publication Year: 1999 , Page(s): 647 - 652
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    Based on a highly accurate current divider using switched current technique without the need of well-matched components, a current reference generator (CRG) circuit is developed to generate and hold the weighed currents used in the data converters. This paper also presents a methodology for designing high-performance CMOS CRG circuits for low-power applications and their performance analysis for estimating the accuracy, speed, and power consumption. To demonstrate the design procedure and performance analysis, several design examples are given. The simulation results show that, for a 6-bit CRG circuit, its calibration time and holding time are 27 and 242 μs, respectively, and for a 8-bit CRG circuit, they are 48 and 236 μs, respectively. The circuit consumes 1.8 mW and achieves better than 10-bit accuracy, where a MOSIS SCNA20 2-μm process and a 3.3-V supply voltage are employed. Thus, the developed CRG circuit is well suited for low-power/low-voltage and moderate resolution data converters View full abstract»

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  • Low-sensitive CCII-based biquadratic filters offering electronic frequency shifting

    Publication Year: 1999 , Page(s): 527 - 539
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    Two novel filter implementations offering electronic frequency shifting are presented. In particular, the first implementation realizes the complete biquadratic function, while the second gives simultaneously high-pass, low-pass, and bandpass second-order transfer functions. The filters are constructed by CCIIs, two of which have tunable current gain employed for frequency shifting. Moreover, we propose design procedures which keep most of the passive and active sensitivities to low values, while diminishing the influence of the parasitic elements existing at the CCII terminals on filter frequency response. The performance of the proposed filters and the effectiveness of the design procedure in minimizing the parasitics effects were examined by PSPICE simulation View full abstract»

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  • Very low-distortion fully differential switched-current memory cell

    Publication Year: 1999 , Page(s): 640 - 643
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    This paper proposes a very low-distortion fully differential switched-current memory cell, based on the opening of the memory switch at a constant voltage. We show that in the previously proposed single-ended Nairn cell, this principle does not lead to low harmonic distortion because the distortion is also a function of the signal-independent clock injection. SPICE simulations indicate that the proposed cell achieves a distortion level of -90 dB to -100 dB, which is about two orders of magnitude below the level achieved with basic switched-current cells. The performance of the proposed cell is near that of state-of-the-art switched-capacitor circuits View full abstract»

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  • Cyclotomic polynomial factorization in finite integer rings with applications to digital signal processing

    Publication Year: 1999 , Page(s): 608 - 616
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    In this paper, results are presented that can be used to obtain all the possible generators for a number theoretic transform (NTT) defined in a finite integer ring and its polynomial extensions. A generalization of the well-known Euler's theorem is derived which can be used to determine all the generators of a given NTT once the generators in the underlying finite field are identified. Based on this extension, a procedure is also described to compute cyclotomic factorization in these rings. This factorization and Chinese remainder theorem lead to computationally efficient algorithms for computing cyclic convolution of two sequences defined in finite and complex integer rings View full abstract»

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  • Automatic analog test signal generation using multifrequency analysis

    Publication Year: 1999 , Page(s): 565 - 576
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    A new multifrequency test generation technique for detecting catastrophic and parametric failures in this class of circuits is presented. Testability transfer factors for circuit elements are introduced and we use them to construct an efficient dynamic test set. Fault detectability and fault coverage are also defined. We also describe the signature analysis methodology used to evaluate the generated test set. Circuits from the suite of analog and mixed-signal benchmark circuits are used to validate our approach. The approach presented may be used to construct input signals for the selection of an external stimulus applied through an arbitrary waveform generator View full abstract»

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  • A new recursive algorithm for multidimensional convolution

    Publication Year: 1999 , Page(s): 652 - 654
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (84 KB)  

    This paper presents a novel recursive algorithm for generating higher order m-dimensional (m-D) convolution by combining the computation of 3m identical lower order (smaller size) convolution computations, and its implementation in parallel VLSI networks. The resulting VLSI architectures have very simple modular structure, highly regular topology, and use simple arithmetic units. Additionally, the proposed architectures have very small depth and contain only a single stage of multipliers, while all other stages contain adders only View full abstract»

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  • Test generation for linear time-invariant analog circuits

    Publication Year: 1999 , Page(s): 554 - 564
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    In this paper, we propose a cost-effective test generation technique for linear time-invariant analog circuits subject to the parametric faults. This technique requires only a small number of test patterns, as opposed to traditional functional testing which utilizes complex stimuli, to classify the circuits. We formulate the test-generation problem as a problem of deriving hyperplanes in the multidimensional space formed by a set of parameters of the device under test (DUT). These hyperplanes define the acceptance region in the measurement space and can be derived by a search-based heuristic. The coefficients of the hyperplanes are then used as test patterns for classification (to determine whether the DUT is in the acceptance region or not). A more general case of using arbitrary “linearly independent” test sequence for classification is also discussed. Experimental results show that less than 10% of misclassification can be achieved by a very small number of tests View full abstract»

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  • Power optimization for pipeline analog-to-digital converters

    Publication Year: 1999 , Page(s): 549 - 553
    Cited by:  Papers (24)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    Power optimization for pipeline analog-to-digital converters (ADCs) is presented. Pipeline ADCs with identical stages, parallel multiplying digital-to-analog converters (MDACs), capacitor scaling and resolution scaling are considered. Given the ratio R between the power consumption by each MDAC and that by each comparator in the sub-ADCs, the optimum bit resolution/stage and the corresponding minimum total power consumption are derived for each architecture. ADCs with capacitor scaling always achieve the lowest minimum power consumption. For ADCs with identical stages with a typical power ratio R of 10 to 20, the optimum number of bits/stage should be three or even four. These results serve as useful guidelines for designers in choosing the optimum number of bits/stage to minimize the ADC's power consumption View full abstract»

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  • A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A/D converter

    Publication Year: 1999 , Page(s): 507 - 516
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    This paper presents a high-speed high-resolution low-power CMOS switched-current cyclic analog-to-digital converter (ADC). The high performance is attributed to the use of the following components: (1) a high-performance residual amplifier which takes two clock cycles to double a current; and (2) an efficient cyclic redundant signed-digit algorithm which provides 1.5 bit resolution without using two matched reference currents. Simulation results show that the developed ADC achieves 12-bit resolution and a conversion rate of 100 ns/bit, where the low-cost MOSIS SCAN20 2 μm CMOS process and 3.3 V supply voltage are employed. The converter has been fabricated and tested, Experimental results on the test chip are also presented. The test chip achieves 12 bit resolution with differential nonlinearity of 0.6 LSB and the integral nonlinearity of 0.5 LSB when operated at a 0.8 Msample/s conversion rate. The power consumption is 1.9 mW View full abstract»

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  • A mismatch-independent DNL pipelined analog-to-digital converter

    Publication Year: 1999 , Page(s): 517 - 526
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    A novel approach for CMOS pipelined analog-to-digital conversion based on switched-capacitor implementation is proposed. This converter's differential nonlinearity (DNL) is independent of any element mismatches in residue amplification. Derivations of the causes on DNL errors in conventional architectures are presented. The DNL of any pipelined converter is dependent upon the conditioning of the residue in the sub-digital-to-analog converter (sub-DAC) and interstage gain stages more than in the choice threshold of the sub-analog-to-digital converter. With well-conditioned residue, any errors made in the sub-DAC's of any earlier stage are evenly distributed over the range of subsequent stages' digital codes. This property is exploited in the design of the proposed converter, which achieves a measured 12 bit resolution and a simulated resolution of 13 bits, even under a 5% mismatch in capacitor ratios. The prototype is implemented using an operational transconductance amplifier with gain boosting. The ADC runs at 10 MHz (3.3 Ms/s) View full abstract»

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  • A new method of frequency compensation for bipolar Wilson current mirror

    Publication Year: 1999 , Page(s): 500 - 506
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    This paper proposes a new method of frequency compensation for a bipolar Wilson current mirror. The mirror is, first, modified: a resistor is inserted into the collector circuit of the diode-connected transistor, and another resistor of equal value is added into the emitter circuit of the same transistor. A compensation capacitor is connected between the collector and base of the feedback transistor. It is shown that the modification produces a pole-zero pair in the current-source transfer function. The split between pole and zero is reduced when the resistor value increases. This results in a wider bandwidth of the mirror transfer function and a faster step-transient response. These improvements are paid for in a small degradation of noise performance View full abstract»

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  • A generalized fast algorithm for n-D discrete cosine transform and its application to motion picture coding

    Publication Year: 1999 , Page(s): 617 - 627
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    In this paper, a generalized fast computational algorithm for the n-dimensional discrete cosine transform (DCT) of length N=2m (m⩾2) is presented. The developed algorithm is proved and its efficiency is evaluated theoretically. The theoretical results show that compared with the conventional method of computing the one-dimensional along n directions, the number of multiplications needed by our algorithm is only 1/n of that required by the conventional method; for the total number of additions, the latter is a bit more when N⩽8 and much fewer when N⩾16 than the former. To validate the proposed algorithm, we take the case when n=3 as an example and apply it to motion-picture coding. The results show that our method is superior to MPEG-2 in speed and coding performance. The algorithm is clearly described and it is easy to make a computer program for implementation View full abstract»

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  • Modeling of CMOS digital-to-analog converters for telecommunication

    Publication Year: 1999 , Page(s): 489 - 499
    Cited by:  Papers (25)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS converter. Matlab is used as a behavior-level simulator. In telecommunications applications, the frequency-domain parameters are of the greatest importance. Therefore, the characterization of the device and its performance is determined by frequency parameters such as the signal-to-noise ratio, spurious-free dynamic range, multitone power ratio, etc. In this paper, we show how these frequency-domain parameters are affected when mismatch errors and finite output impedance are applied to a current-steering CMOS DAC. We discuss how static performance is affected when changing the size of the errors and fundamental circuit parameters. The impact of dynamic errors such as glitches, slewing, and bit skew is discussed. Measurement results from 14-bit DACs are also shown to illustrate the correlation with the modeling View full abstract»

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  • New VLSI array processor design for image window operations

    Publication Year: 1999 , Page(s): 635 - 640
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    A novel architecture named window-memory sharing processor array is proposed, which targets window operations in image processing. The architecture can be used not only for conventional image filtering, but also in practical window operations such as motion vector search in MPEG2. The derived architecture is flexible enough to satisfy user's requirement for either area or speed View full abstract»

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  • A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation

    Publication Year: 1999 , Page(s): 628 - 631
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    This paper presents a 1.5-V CMOS true-single-phase (TSP) bootstrapped dynamic-logic (BDL) circuit using all-N-logic and bootstrapped circuit techniques for high-speed operation at a low supply voltage. As confirmed by the experimental results from the test chip implemented using a 0.8-μm CMOS technology, the speed performance of this CMOS all-N-logic TSP BDL circuit with four serial inputs is 75% faster at a supply voltage of 1.5 V, as compared to the conventional TSP dynamic-logic circuit. Using an all-N-logic TSP BDL circuit, the maximum operating frequency of an implemented digital quadrature modulator is 482 MHz at 5 V, and 68 MHz at 1.5 V, which is 27% faster compared to the circuit without using the BDL circuit View full abstract»

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  • The facilitation of insight for analog design

    Publication Year: 1999 , Page(s): 540 - 548
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4120 KB)  

    The design of an electronic circuit or system-and, indeed, of many other artifacts and schemes-depends heavily upon the expertise, knowledge, and innate skill of the human designer. Unfortunately, many computer based tools fail to fully exploit such human qualities. Thus, while a massive amount of research has been carried out in the essentially technical aspects of circuit design, very little effort has been directed to the support of essentially human aspects of design, such as the development of insight through exploration. This paper describes a new concept, embodied for illustration in a tool called the Influence Explorer, which facilitates human visualization of the relations existing between the parameters and performances of a circuit, thereby enhancing the designer's acquisition of insight into those relations and, as a consequence, the quality of a final design. The new tool is not intended to replace existing computer-aided design tools, but rather to complement them by exploiting a human activity largely unsupported at present View full abstract»

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  • A 155-MHz BiCMOS automatic gain control amplifier

    Publication Year: 1999 , Page(s): 643 - 647
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    This paper proposes a 155-MHz automatic gain control (AGC) amplifier implemented in a double-poly-double-metal 1.0-μm BiCMOS technology. The amplifier contains an exponential-type variable gain amplifier, a buffer-based filter, and asynchronous demodulation peak detector circuits. The initialization and the output magnitude setup circuits are incorporated in the AGC amplifier. It yields an input dynamic range of at least 26 dB and provides a constant output of 1 V pp at a 50-Ω load with AGC loop bandwidth of 80 kHz. The power consumption is 180 mW from a single 5-V supply View full abstract»

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  • Signed power-of-two term allocation scheme for the design of digital filters

    Publication Year: 1999 , Page(s): 577 - 584
    Cited by:  Papers (50)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    It is well known that if each coefficient value of a digital filter is a sum of signed power-of-two (SPT) terms, the filter can be implemented without using multipliers. In the past decade, several methods have been developed for the design of filters whose coefficient values are sums of SPT terms. Most of these methods are for the design of filters where all the coefficient values have the same number of SPT terms. It has also been demonstrated recently that significant advantage can be achieved if the coefficient values are allocated with different number of SPT terms while keeping the total number of SPT terms for the filter fixed. In this paper, we present a new method for allocating the number of SPT terms to each coefficient value. In our method, the number of SPT terms allocated to a coefficient is determined by the statistical quantization step-size of that coefficient and the sensitivity of the frequency response of the filter to that coefficient. After the assignment of the SPT terms, an integer-programming algorithm is used to optimize the coefficient values. Our technique yields excellent results but does not guarantee optimum assignment of SPT terms. Nevertheless, for any particular assignment of SPT terms, the result obtained is optimum with respect to that assignment View full abstract»

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  • High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier

    Publication Year: 1999 , Page(s): 655 - 658
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    In this paper, we propose a fully pipelined two-dimensional (2-D) bit level systolic architecture for efficient implementation of discrete orthogonal transforms using a serial-parallel vector-matrix multiplication scheme based on the Baugh-Wooley algorithm. Apart from its regularity and simplicity, the proposed structure yields high throughput due to massive parallelism across the 2-D mesh. The area- and time-complexities of the proposed structure are (ON2) and O(2nN2), respectively, for implementation of N-point transform, where n is the wordlength View full abstract»

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  • Variable 2-D FIR digital filter design and parallel implementation

    Publication Year: 1999 , Page(s): 631 - 635
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    The frequency response of a variable two-dimensional (2-D) digital filter is specified by several parameters called spectral parameters. The spectral parameters independently control the shapes of the variable frequency response, It is difficult to apply the existing frequency transformation-based methods to design such general variable 2-D filters. This paper proposes a general approach by assuming each filter coefficient as a multidimensional (M-D) polynomial of the spectral parameters, then the optimal coefficients of the M-D polynomials are found in the least squares sense. Also, the paper shows that the resulting variable 2-D filters can be implemented in parallel form, so that parallel signal processing is possible View full abstract»

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  • Design of multichannel QMF banks via frequency-domain optimizations

    Publication Year: 1999 , Page(s): 599 - 607
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    Design of uniform multirate filter banks is studied via frequency domain optimizations. Efficient and reliable design algorithms are developed using state-space computations. In our approach, analysis filter banks are designed to achieve frequency domain specifications dictated by subband coding requirements, and synthesis filter banks are designed to minimize the reconstruction error in frequency domain under the constraint of zero-aliasing error. The design criterion is chosen to be the ℋ or Chebyshev norm. A state-space solution is derived for ℋ, optimization, and numerical algorithms are developed to obtain the optimal-synthesis filter bank. Moreover, the asymptotic perfect reconstruction property (in the sense that time-delay approaches to infinity) is established for the optimal ℋ, solution of the synthesis filter bank. The results in this paper generalize our earlier work for the two channel case to the M-channel case View full abstract»

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  • V-vector algebra and its application to Volterra-adaptive filtering

    Publication Year: 1999 , Page(s): 585 - 598
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    In this paper, we describe a new algebraic structure called V-vector algebra, which is a formal basis for the development of Volterra-adaptive filter algorithms as an extension of linear-adaptive techniques. In this way, fast and numerically stable adaptive Volterra filtering algorithms can be easily derived from the known linear theory. V-vector algebra can also be applied to deal with linear multichannel filters with channels of different memory lengths. A reformulation of the Lee-Mathews fast recursive least squares (RLS) algorithm and a new fast and stable Givens rotation-based square root RLS algorithm, both derived using V-vector algebra, are finally presented View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope