By Topic

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 6 • Date Jun 1999

Filter Results

Displaying Results 1 - 22 of 22
  • Wave digital filter structures for high-speed narrow-band and wide-band filtering

    Publication Year: 1999 , Page(s): 726 - 741
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    Wave digital filter (WDF) structures for high-speed narrow-band and wide-band filtering are introduced. The narrow-band filter is composed of a periodic model filter and one or several, possibly periodic, masking filters in cascade. Lattice and bireciprocal lattice WDF filters are used for the model and masking filters, respectively. The wide-band filter consists of a narrow-band filter in parallel with an all-pass filter. The overall filters can be designed by separately designing the model and masking filters. The filters obtained in this approach also serve as good initial filters for further optimization. Both nonlinear and approximately linear phase filters are considered. One major advantage of the new filters over the corresponding conventional filters is that they have a substantially higher maximal sample frequency. In the case of approximately linear phase, the computational complexity can also be reduced. Further, the use of bireciprocal lattice wave digital (WD) masking filters also makes it possible to reduce the complexity, compared with the case in which FIR masking filters are used. Several design examples and a discussion of finite wordlength effects are included for demonstrating the properties of the new filters View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The impact of induced gate noise when simultaneously power and conjugate noise-matching MOS transistors

    Publication Year: 1999 , Page(s): 842 - 844
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    A method for simultaneously power matching and conjugate noise matching a MOS transistor for radio frequency applications is presented in this paper. Experimental results from a 0.6 μm nMOS transistor show that the magnitude of input reactance equals the optimum noise reactance (i.e., Xin=Xopt). Using this result, the author provides a method that can be used to match the optimum noise resistance to the source resistance. The described method uses the number of gate fingers as a parameter to conjugately match for noise View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A generalized prediction method for modified memory-based high throughput VLC decoder design

    Publication Year: 1999 , Page(s): 742 - 754
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    Variable-length code (VLC) is the most popular data-compression technique which has been used in many data-compression standards, such as JPEG, MPEG-2, and H.263. In this paper, we present a new memory-based tree-search algorithm and very large scale integration architecture for VLC decoders which can achieve very high decoding throughput performance. Different coding tables can be implemented by simply changing the contents of the memory without changing the system hardware. The coding table is mapped onto a memory whose space requirement has been minimized by using a new tree data structure and efficient memory-mapping strategy. In addition, we break the recursive dependency of iterative searching operations by predicting method. The proposed algorithm and architecture can predict the searching node and perform parallel operations. As a result, the decoding throughput rate can be enhanced to about three to eight times more than previously announced architectures. The proposed architecture mainly consists of memory modules and simple arithmetic unit. Based on 0.6-μm single poly triple metal CMOS technology and MPEG-2 VLC table-15, the decoder system achieves average decoding throughput rate of 720 Mbits/s at 3 V and a 100-MHz clock rate View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of switch resistance on the SC integrator settling time

    Publication Year: 1999 , Page(s): 810 - 816
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    Using general feedback theory, a model is developed for the switched-capacitor integrator. This model is then used to analyze the effects of sampling and feedback switch resistances on the integrator settling time. If the frequency corresponding to the sampling time constant is less than five times the frequency of the second pole of the amplifier, the integrator settling time will be degraded. The feedback switch resistance has little effect on the integrator settling time for switch resistances up to 50 kΩ View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 200-MHz CMOS I/Q downconverter

    Publication Year: 1999 , Page(s): 808 - 810
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    This CMOS in-phase/quadrature (I/Q) downconverter circuit is based on a modified sampling architecture which permits very precise I/Q phase and amplitude balance across the entire 200-MHz bandwidth of operation. At a radio frequency of 201 MHz, the downconverter uses a local oscillator sampling rate of 40 MHz and an intermediate frequency of 1 MHz. The circuit is implemented in a 0.5-μm process and has a measured I/Q balance of better than 0.33 dB and 0.7°, with a power consumption of 20 mW from a 3-V supply, and a die area of 0.9 mm2 View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiple operating points in a CMOS log-domain filter

    Publication Year: 1999 , Page(s): 705 - 710
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    A second order bandpass filter was designed by converting a conventional bipolar junction transistor-based log-domain filter circuit to its weak-inversion CMOS equivalent. When biased as designed, the filter performed as expected, but the integrated circuit at times self-biased to an unintended operating point, rendering the circuit useless. This behavior is related to the positive feedback loops used in log domain (and many other) circuits. Such situations cannot, in general, be predicted by inspection of the circuit topology. A method is presented for predicting and analyzing multiple operating points in SPICE circuit simulation. Of course, the method's predictions apply only to the circuit as modeled in the simulator. Detailed analysis illustrates that the number of operating points can depend on the modeling of effects (in this case, well-substrate leakage currents) that are often modeled carelessly, if at all View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sigma-delta ADC with reduced sample rate multibit quantizer

    Publication Year: 1999 , Page(s): 824 - 828
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    Based on the well-known Leslie-Singh architecture, a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multibit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given. The architecture can be a good choice to extend the use of sigma-delta ADC to high bandwidth applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient architectures to recover the regularized least squares solution

    Publication Year: 1999 , Page(s): 828 - 831
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    Several practical applications are concerned with the identification of the least squares (LS) solution. The objective is to attain this solution accurately and efficiently while conserving resources. The computational and storage requirements to determine the LS solution by any iterative procedure become prohibitively large as the problem dimensions grow. This work presents some architectures based on thresholded binary networks which recover regularized LS solutions by partitioning such networks and adopting a switching operation between active and inactive partitions to optimize the objective function. Also, an iterative method based on steepest descent is briefly discussed and implemented. It yields reliable estimates of the regularized LS solution, while providing savings in computation and storage View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analog circuit performance and process scaling

    Publication Year: 1999 , Page(s): 711 - 725
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    With newer CMOS processes, minimum transistor dimensions decrease and the supply voltage steadily gets lower. This trend is driven by the performance of digital systems: their level of performance (speed) increases while at the same time the cost (power consumption and die area) decreases. However, the performance of analog or mixed-signal circuits in newer CMOS generations does not necessarily improve. In this paper, trends in CMOS technology and supply voltage in relation to the performance of analog blocks in mixed-signal chips are analyzed. First, a relation for the absolute minimum power consumption of analog circuits is derived, based on a specific signal-to-noise and-distortion ratio (SINAD) over the full signal bandwidth. This limit shows that power consumption increases considerably with decreasing supply voltage, even at a constant performance level. The second part of this paper illustrates the trend in power consumption for actual analog circuits with SINAD demands. A quasi-differential CMOS voltage-follower circuit is used as a demonstration vehicle. In newer CMOS processes, the MOS transistors in the circuit get better, which tends to decrease the power consumption. The combined effect of the improving MOS transistors and the decreasing supply voltage is that power consumption at constant performance decreases down to about the 0.25-0.35-μm CMOS generations, and increases with newer CMOS generations thereafter. Ultimately, low supply voltages limit circuit feasibility or performance feasibility of analog circuits in newer CMOS processes View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New multifunction OTA-C biquads

    Publication Year: 1999 , Page(s): 820 - 824
    Cited by:  Papers (47)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    Some novel multifunction biquadratic filters, each of which employs two to three operational transconductance amplifiers and two capacitors, are presented. Each proposed circuit offers the following advantageous features: realization of different biquadratic filter signals from the same configuration, no requirements for component-matching conditions, employment of only two capacitors, control of ωo and ωo/Q, with separate tunable transconductances and low sensitivities View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Circuit requirements of a direct conversion paging receiver

    Publication Year: 1999 , Page(s): 802 - 807
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    Circuit requirements of a direct-conversion FLEX paging receiver with the zero-crossing interpolation demodulator are derived by means of high-level simulation. Impacts of the limitations on noise and nonlinearity characteristics of the radio frequency (RF) stage, the in-phase and quadrature-phase mismatch, and the local oscillator frequency drift are analyzed relative to the degradation of the bit error rate. Official specifications on radio paging receivers are introduced to ensure the minimum performance. It is shown that an RF front-end with 25-dB gain, 5.3-dB noise figure, and 11-dBm second order intercept point makes the receiver qualified for the sensitivity, desensitization, and intermodulation requirements View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pulse-based 2-D motion sensors

    Publication Year: 1999 , Page(s): 677 - 687
    Cited by:  Papers (29)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    We present two compact CMOS integrated circuits for computing the two-dimensional (2-D) local direction of motion of an image focused directly onto the chip. These circuits incorporate onboard photoreceptors and focal plane motion processing. With fully functional 14×13 and 12×13 implementations consuming less than 50 μW per pixel, we conclude that practical pixel resolutions of at least 64×64 are easily achievable. Measurements characterizing the elementary one-dimensional motion detectors are presented along with a discussion of 2-D performance and example 2-D motion vector fields. As an example application of the sensor, it is shown that the array as fabricated can directly compute the focus of expansion of a 2-D motion vector field View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A blind fractionally spaced equalizer using higher order statistics

    Publication Year: 1999 , Page(s): 755 - 764
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    In this paper, we introduce a new blind fractionally spaced equalizer based on the fourth-order statistics of the input symbol sequence. The input symbol sequence is assumed to come from an independent identically distributed finite alphabet with nonzero fourth-order cumulants. We formulate the equalizer as a column vector and compute it by simultaneously diagonalizing a set of matrices obtained from the fourth-order cross-cumulants of the input and output of the equalizer. Simulation results show that this equalizer works well with a short symbol sequence, even if the channel time span is not accurately estimated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Limit-cycle oscillations in a log-domain-based filter

    Publication Year: 1999 , Page(s): 832 - 836
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    A circuit is presented for a class-AB fully differential log-domain parallel resonator based on a capacitively loaded gyrator. It is shown that if floating rather than shunt capacitive loads are used, the circuit is stable for small stimuli, but can be triggered into steady-state limit-cycle oscillations by large enough transient inputs. The nature of the instability is explored and it is shown how SPICE transient analysis can be used to detect the instability and locate the separatrix between stable-equilibrium-point-seeking and limit-cycle-seeking regions of state space. Analysis is also presented to demonstrate that the circuit with floating capacitors does not implement an externally linear transfer function, and therefore, it is not a true log-domain circuit View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel adaptive mismatch cancellation system for quadrature IF radio receivers

    Publication Year: 1999 , Page(s): 789 - 801
    Cited by:  Papers (89)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    This paper investigates and resolves in-phase/quadrature phase (I/Q) imbalances between the input paths of quadrature IF receivers. These mismatches along the paths result in the image interference aliasing into the desired signal band, thus reducing the dynamic range and degrading the performance of the receivers. I/Q errors occur because of gain and phase imbalances between quadrature mixers. They are also caused by capacitor mismatches in analog-to-digital converters (A/Ds), which are designed to be identical for each input path. This paper presents a novel and feasible digital signal processing (DSP) solution for the I/Q mismatch problems. The system includes a novel complex least mean square algorithm and a modified adaptive noise canceler (signal separator) to separate the desired signal and the image noise caused by the mismatch. The noise canceler can also solve the signal leakage problem, which is that the noise reference includes signal components. This system was implemented in a Xilinx FPGA and an Analog Devices DSP chip. It was tested with a complex intermediate frequency receiver, which includes an analog front end and a complex sigma-delta modulator. Both simulation results and test results show a dramatic attenuation of the image noise. Extending applications of the system to N-path systems further indicates the robustness and feasibility of this novel adaptive mismatch cancellation system View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient training of neural gas vector quantizers with analog circuit implementation

    Publication Year: 1999 , Page(s): 688 - 698
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    This paper presents an algorithm for training vector quantizers with an improved version of the neural gas model, and its implementation in analog circuitry. Theoretical properties of the algorithm are proven that clarify the performance of the method in terms of quantization quality, and motivate design aspects of the hardware implementation. The architecture for vector quantization training includes two chips, one for Euclidean distance computation, the other for programmable sorting of codevectors. Experimental results obtained in a real application (image coding) support both the algorithm's effectiveness and the hardware performance, which can speed up the training process by up to two orders of magnitude View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Semi-infinite linear programming: a unified approach to digital filter design with time- and frequency-domain specifications

    Publication Year: 1999 , Page(s): 765 - 775
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    Using the recently developed semi-infinite linear programming techniques and Caratheodory's dimensionality theory, we present a unified approach to digital filter design with time and/or frequency-domain specifications. Through systematic analysis and detailed numerical design examples, we demonstrate that the proposed approach exhibits several salient features compared to traditional methods: 1) using the unified approach, complex responses can be handled conveniently without resorting to discretization; 2) time domain constraints can be included easily; and 3) any filter structure, recursive or nonrecursive, can be employed, provided that the frequency response can be represented by a finite-complex basis. More importantly, the solution procedure is based on the numerically efficient simplex extension algorithms. As numerical examples, a discrete-time Laguerre network is used in a frequency-domain design with additional group-delay specifications, and in a ℋ-optimal envelope constrained-filter design problem. Finally, a finite impulse response phase equalizer is designed with additional frequency domain ℋ robustness constraints View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of low-error fixed-width multipliers for DSP applications

    Publication Year: 1999 , Page(s): 836 - 842
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    In this work, two designs of low-error fixed-width sign-magnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2 n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low error reduced-width multiplier with output bit-width between n- and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise analysis for sampling mixers using stochastic differential equations

    Publication Year: 1999 , Page(s): 699 - 704
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    We analyze three different sources of noise in a sampling mixer working at radio frequency (RF) or intermediate frequency. External RF and intrinsic noise are analyzed using conventional frequency domain methods. External local oscillator (LO) noise is analyzed in the time domain by solving a stochastic differential equation. We are able to take into account the time varying aspect of the LO noise coupling, and show that LO noise becomes important at high frequencies. An analytical expression for LO noise is obtained, which can be used to guide mixer design. LO noise is in addition to LO jitter, which should be combined with noise analysis to give a complete picture View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-voltage rail-to-rail CMOS V-I converter

    Publication Year: 1999 , Page(s): 816 - 820
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    This paper presents CMOS low-voltage rail to-rail voltage-to-current (V-I) converters which could be used as basic building blocks to construct low-voltage current-mode analog very large scale integration (VLSI) circuits. In the circuit, an n-type V-I converter cell is connected in parallel with its p-type counterpart to achieve common-mode rail to-rail operation. A linear differential relationship of the n-type V-I converter, or its p-type complement, is obtained using a new class-AB linearization technique. The constant transconductance value is obtained by manipulating the DC bias currents of n- and p-type V-I converter cells. The circuit can operate from rail to rail with a power supply of 3 V or less, depending on the VLSI technology and the DC bias current level View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Clock jitter and quantizer metastability in continuous-time delta-sigma modulators

    Publication Year: 1999 , Page(s): 661 - 676
    Cited by:  Papers (100)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    The performance of continuous-time (CT) delta-sigma modulators (ΔΣM's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT ΔΣM clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT ΔΣM given jitter and metastability constraints View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Decorrelating (DECOR) transformations for low-power digital filters

    Publication Year: 1999 , Page(s): 776 - 788
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    Decorrelating transformations (referred to as DECOR transformations) to reduce the power dissipation in digital filters are presented in this paper. The transfer function and/or the input is decorrelated such that fewer bits are required to represent the coefficients and inputs. Thus, the size of the arithmetic units in the filter is reduced, thereby reducing the power dissipation. The DECOR transform is suited for narrow-band filters because there is significant correlation between adjacent coefficients. Simulations with fixed coefficient filters indicate reduction in transition activity, ranging from 6% to 52% for filter bandwidths ranging from 0.30 π to 0.05 π, respectively, (where π corresponds to half the sample rate). Simulations with adaptive filters indicate reduction in transition activity in the F-block, ranging from 12% to 38% for filter bandwidths ranging from 0.30 π to 0.05 π, respectively. The DECOR transforms result in greater energy savings and over a larger bandwidth than existing methods View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope