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Circuits and Systems for Video Technology, IEEE Transactions on

Issue 4 • Date Aug 1998

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Displaying Results 1 - 12 of 12
  • A novel unrestricted center-biased diamond search algorithm for block motion estimation

    Publication Year: 1998 , Page(s): 369 - 377
    Cited by:  Papers (276)  |  Patents (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    The widespread use of block-based interframe motion estimation for video sequence compression in both MPEG and H.263 standards is due to its effectiveness and simplicity of implementation. Nevertheless, the high computational complexity of the full-search algorithm has motivated a host of suboptimal but faster search strategies. A popular example is the three-step search (TSS) algorithm. However, its uniformly spaced search pattern is not well matched to most real-world video sequences in which the motion vector distribution is nonuniformly biased toward the zero vector. Such an observation inspired the new three-step search (NTSS) which has a center-biased search pattern and supports a halfway-stop technique. It is faster on average, and gives better motion estimation as compared to the well-known TSS. Later, the four-step search (4SS) algorithm was introduced to reduce the average case from 21 to 19 search points, while maintaining a performance similar to NTSS in terms of motion compensation errors. We propose a novel unrestricted center-biased diamond search (UCBDS) algorithm which is more efficient, effective, and robust than the previous techniques. It has a best case scenario of only 13 search points and an average of 15.5 block matches. This makes UCBDS consistently faster than the other suboptimal block-matching techniques. This paper also compares the above methods in which both the processing speed and the accuracy of motion compensation are tested over a wide range of test video sequences View full abstract»

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  • POCS-based error concealment for packet video using multiframe overlap information

    Publication Year: 1998 , Page(s): 422 - 434
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    This paper proposes a new error concealment algorithm for packet video, effectively eliminating error propagation effects. Most standard video codecs use motion compensation to remove temporal redundancy. With such motion-compensated interframe processing, any packet loss may generate serious error propagation over more than ten consecutive frames. This kind of error propagation leads to perceptually annoying artifacts. Thus, proper error concealment algorithms need to be used to reduce this effect. The proposed algorithm adopts a one-pixel block overlap structure. With the redundancy information from the damaged frame and the following frames, the proposed POCS-based method can have consistently high performance in error concealment. According to the experimental results, the proposed algorithm can successfully eliminate visible error propagation. In addition, the proposed algorithm is very robust. Experimental results show that it can have good error concealment results, even when the damaged frame loses all the DCT coefficients View full abstract»

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  • Interpolation-free subpixel motion estimation techniques in DCT domain

    Publication Year: 1998 , Page(s): 460 - 487
    Cited by:  Papers (11)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1248 KB)  

    Currently existing subpixel motion estimation algorithms require interpolation of interpixel values which undesirably increases the overall complexity and data flow and deteriorates the estimation accuracy. We develop discrete cosine transform (DCT)-based techniques to estimate subpel motion at different desired subpel levels of accuracy in the DCT domain without interpolation. We show that subpixel motion information is preserved in the DCT of a shifted signal under some condition in the form of pseudophases, and we establish subpel sinusoidal orthogonal principles to extract this information. The proposed subpixel techniques are flexible and scalable in terms of estimation accuracy with very low computational complexity O(N2 ) compared to O(N4) for the full-search block-matching approach and its subpixel versions. Above all, motion estimation in the DCT domain instead of the spatial domain simplifies the conventional hybrid DCT-based video coder, especially the heavily loaded feedback loop in the conventional design, resulting in a fully DCT-based high-throughput video codec. In addition, the computation of pseudophases is local, and thus a highly parallel architecture is feasible for the DCT-based algorithms. Finally, simulation on video sequences of different characteristics shows comparable performance of the proposed algorithms to block-matching approaches View full abstract»

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  • A lightweight genetic block-matching algorithm for video coding

    Publication Year: 1998 , Page(s): 386 - 392
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    A lightweight genetic search algorithm (LGSA) is proposed. Different evolution schemes are investigated, such that the control overheads are largely reduced. It is also shown that the proposed LGSA can be viewed as a novel expansion of the three-step search algorithm (TSS). It can be seen from the simulation results that the performance of LGSA is very similar to that of the full search algorithm (FSA), and the computational complexity is much lower than that of FSA and other previously proposed genetic motion estimation algorithms View full abstract»

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  • Approximate convolution using DCT coefficient multipliers

    Publication Year: 1998 , Page(s): 378 - 385
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    We develop a method for designing discrete cosine transform (DCT) coefficient multipliers in order to approximate the operation of two-dimensional (2-D) convolution of an image with a given kernel. The method is easy to implement on compressed formats of DCT-based compression methods (JPEG, MPEG, H.261) by using decoding quantization tables that are different from the encoding quantization tables View full abstract»

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  • Adaptive quantization and fast error-resilient entropy coding for image transmission

    Publication Year: 1998 , Page(s): 411 - 421
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    There has been an outburst of research in image and video compression for transmission over noisy channels. Channel matched source quantizer design has gained prominence. Further, the presence of variable-length codes in compression standards like the JPEG and the MPEG has made the problem more interesting. Error-resilient entropy coding (EREC) has emerged as a new and effective method to combat catastrophic loss in the received signal due to burst and random errors. We propose a new channel-matched adaptive quantizer for JPEG image compression. A slow, frequency-nonselective Rayleigh fading channel model is assumed. The optimal quantizer that matches the human visibility threshold and the channel bit-error rate is derived. Further, a new fast error-resilient entropy code (FEREC) that exploits the statistics of the JPEG compressed data is proposed. The proposed FEREC algorithm is shown to be almost twice as fast as EREC in encoding the data, and hence the error resilience capability is also observed to be significantly better. On average, a 5% decrease in the number of significantly corrupted received image blocks is observed with FEREC. Up to a 2-dB improvement in the peak signal-to-noise ratio of the received image is also achieved View full abstract»

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  • Efficient cost measures for motion estimation at low bit rates

    Publication Year: 1998 , Page(s): 488 - 500
    Cited by:  Papers (9)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    We present and compare methods for choosing motion vectors for block-based motion-compensated video coding. The primary focus is on videophone and videoconferencing applications, where low bit rates are necessary, where motion is usually limited, and where the amount of computation is also limited. In a typical block-based motion-compensated video coding system, motion vectors are transmitted along with a lossy encoding of the residuals. As the bit rate decreases, the proportion required to transmit the motion vectors increases. We provide experimental evidence that choosing motion vectors explicitly to minimize rate (including motion vector coding), subject to implicit constraints on distortion, yields better rate-distortion tradeoffs than minimizing some measure of prediction error. Minimizing a combination of rate and distortion yields further improvements. Although these explicit-minimization schemes are computationally intensive, they provide invaluable insight which we use to develop practical algorithms. We show that minimizing a simple heuristic function of the prediction error and the motion vector code length results in rate-distortion performance comparable to explicit-minimization schemes while being computationally feasible. Experimental results are provided for coders that operate within the H.261 standard View full abstract»

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  • A linear array processor with dynamic frequency clocking for image processing applications

    Publication Year: 1998 , Page(s): 435 - 445
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    The need for high-performance image processing systems has led to the design and development of several application-specific parallel processing systems. An SIMD linear array processor with dynamic frequency clocking is proposed for real-time image processing applications. The architecture uses a novel concept called dynamic frequency clocking which allows the processor to vary the clock frequency dynamically based on the operation being performed. A VLSI chip based on the proposed architecture has been designed and verified using the Cadence design tools. The chip will operate at between 400 and 50 MHz based on the operation being performed. Several low-level image processing tasks have been mapped onto the architecture to evaluate the system performance and to demonstrate the effectiveness of the dynamic frequency clocking scheme View full abstract»

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  • Interframe coding using two-stage variable block-size multiresolution motion estimation and wavelet decomposition

    Publication Year: 1998 , Page(s): 399 - 410
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    We propose a two-stage variable block-size multiresolution motion estimation (MRME) algorithm. In this algorithm, a method to reduce the amount of motion information is developed, and a bit allocation method minimizing the sum of the motion information and the prediction error is obtained in the wavelet transform domain. In the first stage of the proposed scheme, we utilize a set of wavelet components of the four subbands in the lowest resolution. These motion vectors are directly used as motion vectors for the lowest subband, and are scaled into the initial biases for other subbands at every layer of the wavelet pyramid. In the second stage, the bottom-up construction of a quadtree based on the merge operation is performed. The proposed scheme reduces the uncompressed bit rate of 8 bits/pixel into 0.212 bits/pixel at 41.1 dB of PSNR for the “Claire” sequence, which can be regarded as nearly an 11% reduction compared with the conventional method View full abstract»

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  • A low-power VLSI architecture for full-search block-matching motion estimation

    Publication Year: 1998 , Page(s): 393 - 398
    Cited by:  Papers (58)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    This paper presents an architectural enhancement to reduce the power consumption of the full-search block-matching (FSBM) motion estimation. Our approach is based on eliminating unnecessary computation using conservative approximation. Augmenting the estimation technique to a conventional systolic-architecture-based VLSI motion estimation reduces the power consumption by a factor of 2, while still preserving the optimal solution and the throughput. A register-transfer level implementation as well as simulation results on benchmark video clips are presented View full abstract»

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  • Bit-rate control using piecewise approximated rate-distortion characteristics

    Publication Year: 1998 , Page(s): 446 - 459
    Cited by:  Papers (116)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    Digital video's increased popularity has been driven to a large extent by a flurry of international standards (MPEG-1, MPEG-2, H.263, etc). In most standards, the rate control scheme, which plays an important role in improving and stabilizing the decoding and playback quality, is not defined, and thus different strategies can be implemented in each encoder design. Several rate-distortion (R-D)-based techniques have been proposed aimed at the best possible quality for a given channel rate and buffer size. These approaches are complex because they require the R-D characteristics of the input data to be measured before making quantization assignment decisions. We show how the complexity of computing the R-D data can be reduced without significantly reducing the performance of the optimization procedure. We propose two methods which provide successive reductions in complexity by: (1) using models to interpolate the rate and distortion characteristics, and (2) using past frames instead of current ones to determine the models. Our first method is applicable to situations (e.g., broadcast video) where a long encoding delay is possible, while our second approach is more useful for computation-constrained interactive video applications. The first method can also be used to benchmark other approaches. Both methods can achieve over 1 dB peak signal-to-noise rate (PSNR) gain over simple methods like the MPEG Test Model 5 (TM5) rate control, with even greater gains during scene change transitions. In addition, both methods make few a priori assumptions and provide robustness in their performance over a range of video sources and encoding rates. In terms of complexity, our first algorithm roughly doubles the encoding time as compared to simpler techniques (such as TM5). However, the complexity is greatly reduced as compared to methods which exactly measure the R-D data. Our second algorithm has a complexity marginally higher than TM5 and a PSNR performance slightly lower than that of the first approach View full abstract»

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  • A design study of a 0.25-μm video signal processor

    Publication Year: 1998 , Page(s): 501 - 519
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    This paper presents a detailed design study of a high-speed, single-chip architecture for video signal processing (VSP), developed as part of the Princeton VSP Project. In order to define the architectural parameters by examining the area and delay tradeoffs, we start by designing parameterizable versions of key modules, and we perform VLSI modeling experiments in a 0.25 μm process. Based on the properties of these modules, we propose a VLIW (very long instruction word) VSP architecture that features 32-64 operations per cycle at clock rates well in excess of 600 MHz, and that includes a significant amount of on-chip memory. VLIW architectures provide predictable, efficient, high performance, and benefit from mature compiler technology. As explained, a VLIW video processor design requires flexible, high-bandwidth interconnect at fast cycle times, and presents some unique VLSI tradeoffs and challenges in maintaining high clock rates while providing high parallelism and utilization View full abstract»

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Aims & Scope

The emphasis is focused on, but not limited to:
1. Video A/D and D/ A
2. Video Compression Techniques and Signal Processing
3. Multi-Dimensional Filters and Transforms
4. High Speed Real-Tune Circuits
5. Multi-Processors Systems—Hardware and Software
6. VLSI Architecture and Implementation for Video Technology 

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dan Schonfeld
Multimedia Communications Laboratory
ECE Dept. (M/C 154)
University of Illinois at Chicago (UIC)
Chicago, IL 60607-7053
tcsvt-eic@tcad.polito.it

Managing Editor
Jaqueline Zelkowitz
tcsvt@tcad.polito.it