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Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 3 • Date Aug 1998

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Displaying Results 1 - 13 of 13
  • Ultra low loss millimeter wave multichip module interconnects

    Publication Year: 1998 , Page(s): 302 - 308
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    We present the design and electrical characterization of a multilayer organic based multichip module (MCM) for use at W-band (75-110 GHz). The ultra-low loss microstrip transmission line on Kapton E(R) (a trademark of DuPont) thin films and benzocyclobutene (BCB) adhesives is reported at W-band. An electrical model for a vertically stacked via interconnect to an integrated circuit (IC) is experimentally developed. This interconnect exhibits very low parasitics and preserves excellent matched conditions for devices and circuits in a module. The electrical performance of the vertically stacked via offers superior performance relative to ribbon and wire bond results reported in the literature at millimeter wave frequencies. We conclude that this technology is capable of realizing compact modules at millimeter wave frequencies View full abstract»

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  • A new approach for the modeling and simulation of electromagnetic interference

    Publication Year: 1998 , Page(s): 216 - 224
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    A new approach for the time-domain analysis of transmission line systems exposed to external fields is presented. The influence of the external field is modeled as an additional fictitious line in the system. The differential equations describing the externally disturbed transmission line system are solved analytically and the parameters of the fictitious line are calculated. Simulations for different line systems in different external fields have been performed. The comparisons with the exact, analytically calculated values demonstrate that this new approach is suitable to accurately model the influence of an external field. The approach is robust enough to make it compatible with virtually any line model and circuit simulator View full abstract»

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  • S/390 cost performance considerations for MCM packaging choices

    Publication Year: 1998 , Page(s): 286 - 297
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    In this paper, we develop a cost performance metric for the comparison of MCM structures used for the packaging of the central electronic complex (CEC) of the S/390 systems. The approach is simple and general enough that it can be used to evaluate any first level package structure. The cost component is based on relative costs for the structures examined, while the performance is estimated through closed form formulae and simulation data of actual products. The results of this comparison show that a glass ceramic MCM with polyimide redistribution is the package of choice for bus frequencies larger than 160 MHz. For bus frequencies less than 160 MHz, all alternatives examined are cost performance equivalent and the choice should be based on other criteria that are application specific View full abstract»

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  • Dynamic analysis of V transmission lines

    Publication Year: 1998 , Page(s): 250 - 257
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    In this work, a dynamic analysis of the V line is presented. Previous work analyzed the performance of this structure for low frequency applications using quasistatic approximations. Here, we extend the analysis of the V line into the higher frequency range where dispersion becomes significant and where it cannot be predicted by quasistatic methods. We show that the V line provides features and advantages that are not present in the conventional microstrip structures, most notably the appreciable decrease in coupling between adjacent lines in comparison with the conventional microstrip structure. This feature makes the V line well suited for high packaging density applications. The full-wave analysis is carried out using a Yee-cell based finite-difference time-domain (FDTD) method, while enforcing a highly efficient and stable mesh truncation technique. Results are presented for a single and multiconductor structures View full abstract»

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  • Composite and multilayered TaOx-TiOy high dielectric constant thin films

    Publication Year: 1998 , Page(s): 274 - 280
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    A novel low temperature deposition process using reactive pulsed dc magnetron sputtering has been developed to deposit thin dielectric films composed of either a composite or alternating layers of tantalum oxide and titanium oxide. Capacitors fabricated from these dielectric materials have been found to exhibit exceptional electrical properties. For the composite material, one film containing 22% TiOy had a high dielectric constant of 38, a leakage current density of 10-6 A/cm2 at 0.5 MV/cm, and a relatively high breakdown field strength of 2.3 MV/cm. By a slight modification of the deposition conditions, alternating layers of tantalum oxide and titanium oxide were deposited to form a high dielectric constant material. The electric at properties of these films were also exceptional: a dielectric constant of 44, a leakage current density of 3.4·10-8 A/cm2 at 0.5 MV/cm, and a breakdown field strength of 2.3 MV/cm. These films have potential applications in memory and advanced electronics packaging View full abstract»

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  • Interconnect and circuit modeling techniques for full-chip power supply noise analysis

    Publication Year: 1998 , Page(s): 209 - 215
    Cited by:  Papers (76)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    This paper describes the interconnect and circuit modeling techniques to analyze the on-chip power supply noise for high-performance very large scale integration (VLSI) design. To reduce the complexity of full-chip analysis, a hierarchical power supply distribution model, which consists of a 12×12 package model, a 50×50 on-chip power bus model, and a distributed switching circuit model, is developed. This integrated chip-and-package model provides a complete analysis of the resistive IR drop, inductive delta-I noise, and the on-chip Vdd distribution. It also allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise. Analysis results of our benchmark microprocessor chips will be presented to demonstrate the various applications of this methodology View full abstract»

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  • Design methodology for chip-on-chip applications

    Publication Year: 1998 , Page(s): 298 - 301
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    Chip-on-chip is a viable alternative solution for some applications requiring logic and memory integration. However, one of the impediments to this technology is lack of design infrastructure. Conventional multichip design methodologies which are extensions of standard board designs are not well-suited to chip-on-chip designs. To address this issue, we have implemented a chip-on-chip design methodology that incorporates both logic and memory design database and utilizes an auto-router to minimize routing layers. It emulates a two-layer routing system by using a single redistribution metal layer on each chip and solder bumps as vias. In this paper, we describe several chip-on-chip modules designed using this methodology and discuss the method's limitations View full abstract»

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  • Characterization of a planar spiral inductor on a composite-resin low-impedance substrate and its application to microwave circuits

    Publication Year: 1998 , Page(s): 269 - 273
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    The Q-factors of planar spiral inductors built on a polyimide-SiO 2-Si substrate are characterized as a function of the polyimide thickness. We found that inductor quality as high as that on a GaAs-microwave and millimeter-wave integrated circuit (MMIC) requires a polyimide thickness of over 100 μm, resulting in a Q-factor of over 17. The applicability of a low-impedance substrate was confirmed through the investigation of a novel RF-MCM in a face-up-type structure for cellular phone systems using a composite epoxy resin-metallic substrate. A fabricated power amplifier module exhibited 28.5-dBm output power and 16% power efficiency at 1.75 GHz View full abstract»

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  • A technique for fast calculation of capacitance matrices of interconnect structures

    Publication Year: 1998 , Page(s): 241 - 249
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    A finite difference (FD) method for rapid and accurate evaluation of capacitance matrices of interconnect configurations is described in this paper. The method utilizes newly-developed perfectly matching layer (PML) technique for mesh truncation, specially adapted to the static case in conjunction with a mixed boundary condition, referred to as the α-technique. The application of proposed approach to the modeling of complex structures, comprising multiple metal layers, cross-overs, vias, and bends embedded in a layered dielectric medium, is illustrated in the paper. The paper also shows the usefulness of the technique to the problem of mapping within the interconnect. A novel approach for efficient truncation of a class of large interconnects called the wraparound scheme, is introduced in the paper. Several numerical examples that illustrate the efficiency and flexibility of the approaches, described above, are included in the paper View full abstract»

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  • Characterization of embedded passives using macromodels in LTCC technology

    Publication Year: 1998 , Page(s): 258 - 268
    Cited by:  Papers (18)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    This paper discusses the frequency and time domain response of embedded passive components in a multilayered structure fabricated using low temperature co-fired ceramic (LTCC) technology. A rational polynomial approximation that combines the accuracy of EM solvers with interpolation methods has been used to capture the frequency dependent losses and parasitics of embedded passives in a macro-model. This method allows for a significant speed-up in computation time while using commercial EM solvers. The macromodel with suitable modification has been used to compute the time domain response in SPICE for typical embedded passive structures. Simulation results show good correlation with time domain reflectometry/time-domain-transmission (TDR/TDT) measurements. The behavior of embedded passives in the high frequency operation of transmission lines and voltage divider networks has also been discussed View full abstract»

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  • Automatic generation of accurate circuit models of 3-D interconnect

    Publication Year: 1998 , Page(s): 225 - 240
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    In order to optimize high-speed systems, designers need tools that automatically generate reduced order SPICE compatible models from geometric descriptions of interconnect and packaging. In this paper, we consider structures small compared to a wavelength, and use a discretized integral formulation combined with an Arnoldi-based model-order reduction strategy to compute efficiently accurate reduced-order models from three-dimensional (3-D) structures. Several issues are addressed including: (1) formulation to insure passivity in the reduced-order models; (2) efficient reduction using preconditioned inner-loop iterative methods; (3) expansion about multiple s-domain points. Results are presented on several industrial examples to demonstrate the capabilities and speed of these new methods View full abstract»

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  • Figures-of-merit for package electrical roadmaps

    Publication Year: 1998 , Page(s): 281 - 285
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    Transient currents created by on-chip switching in cores and by off-chip drivers cause noise to be generated on package parasitics. Simple mathematical models for the noise are used to derive figures-of-merit for the two cases of on-chip and off-chip switching. SIA Roadmap packaging trends are used with the figures-of-merit to produce package noise trends View full abstract»

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  • Low-cost AlGaAs/GaAs HBT multi-gigabit limiting amplifier packaged with a new plastic air tight cavity encapsulation process

    Publication Year: 1998 , Page(s): 309 - 313
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    A multigigabit limiting amplifier integrated circuit (IC) for optical transmission system was implemented with AlGaAs HBT technology and packaged in a plastic-molded-bottom-ground air-cavity package using an alpha-staged thermally setting epoxy which comes in a gel in an uncured state. The amplifier was designed to support differential input and output. Small signal performance of the packaged IC achieves 31 dB gain and f3 dB of 4.6 GHz. A single output has 1.0 Vp-p swing with more than 32 dB dynamic range up to 5 Gb/s. The measured bit error rate applying to APD optical receiver at 2.5 Gb/s bit rate is -33.5 dBm at 1×10-10 BER with 223-1 long 2.5 Gb/s NRZ PRBS pattern. The present packaging method was verified by subjecting it to the industry standard condition “c” gross leak test and the overall yield of the air cavity encapsulation process is more than 99%. This method is readily capable of mass production using automated equipment View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope