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Signal Processing Magazine, IEEE

Issue 2 • Date March 1998

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Displaying Results 1 - 6 of 6
  • VLIW Architecture For Media Processing

    Publication Year: 1998 , Page(s): 16 - 19
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (422 KB)  

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  • The impact of Mpact 2

    Publication Year: 1998 , Page(s): 102 - 107
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    Mpact media processors enable powerful, flexible and cost-effective multimedia in a PC. A single chip replaces today's multiboard, multichip solutions for graphics, video, audio, and communications. The architecture combines a high-bandwidth RAMBUS memory, VLIW/SIMD (single instruction, multiple data) processing, standard buses, and software programmability for the cost of a modern graphics chip. Mpact architecture uses a modified VLIW style with two RISC-like instructions per VLIW. The instructions are either executed sequentially or concurrently based on a tag in the VLIW. Classical VLIW suffers from low code density due to unused instruction fields, but the Mpact modified VLIW has the same code density as RISC instructions. Additionally, the SIMD instructions improve code density by increasing the work done by each instruction. An 8 byte word size was chosen to balance vector and scalar performance and also to balance data and instruction bandwidth. A 9 bit byte was chosen to represent color-component differences in one byte and to represent 18 bit color or 18 bit audio samples in two bytes. Hardware-dithered rounding of quantization noise allows most audio to be processed in two byte precision. The maximal multiplier precision of 24×24 was chosen for audio requirements. The article reviews the first-generation Mpact media processor and then describes the multimedia performance goals and architecture of Chromatic's second-generation media processor architecture. It then presents newer modules of the architecture in more detail View full abstract»

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  • The latest word in digital and media processing

    Publication Year: 1998 , Page(s): 59 - 85
    Cited by:  Papers (20)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3628 KB)  

    The article discusses the technology behind the resurgence of DSP oriented microprocessors and the techniques that allow one to use them well. After an overview of the VLIW architecture, it discusses three main areas: VLIW architectural feature relevant to DSP applications; their associated complier techniques; and coding techniques that allow the application programmer, while still coding in a high-level language, to best exploit the architecture View full abstract»

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  • Processing the new world of interactive media

    Publication Year: 1998 , Page(s): 108 - 117
    Cited by:  Papers (10)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1020 KB)  

    Trimedia is a family of programmable multimedia processors from the Trimedia product group of Philips Semiconductors. This architecture is based upon a high-performances VLIW CPU core. TM-1000 is the first product from a family of multimedia processors based upon the Trimedia architecture. TM-1000 is designed to concurrently process video, audio, graphics, and communication data. TM-1000 consists of a high-performance VLIW-based CPU core, large instruction and data caches, main memory interface, and video, audio and communication related peripherals. TM-1000 is a multimedia system on a chip: high-quality video and audio applications can be implemented in TM-1000 using high-level languages such as “C” and “C++”. The authors mainly focus on the VLIW CPU architecture View full abstract»

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  • The past, present, and future of image and multidimensional signal processing

    Publication Year: 1998 , Page(s): 21 - 58
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (11304 KB)  

    The field of image and multidimensional signal processing began as a field of strong theoretical framework based on mathematics, statistics, and physics. Later, with advances in computing, memory, and image-sensing technology, techniques developed for image enhancement, still and moving image compression, image understanding gave this field a solid base of practical applications. Furthermore, the exploding growth of the Internet and the ubiquity of images and video, the field of image and multidimensional signal processing is becoming more and more exciting. Topics covered in the article include: multidimensional signal-processing theory, image acquisition, image transforms, image modeling, image enhancement and restoration, image and video analysis, processing, coding, hardware and software implementation issues, and computed imaging View full abstract»

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  • High VelociTI processing [Texas Instruments VLIW DSP architecture]

    Publication Year: 1998 , Page(s): 86 - 101, 117
    Cited by:  Papers (14)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1968 KB)  

    The Texas Instruments VelociTI architecture is a very long instruction word (VLIW) architecture. The TMS320C6x family of digital signal processors (DSPs) is the first to employ the VelociTI architecture, with the TMS3206201 (C6201) being the first device in this family. The C6201 is based on the fixed-point TMS320C62x (C62x) CPU. This article describes the VelociTI VLIW architecture and discusses the C62x, C67x, C6201, and the VelociTI development tools. An overview of the VelociTI including architectural principles, data path, instruction set, and pipeline operation is presented, and both the C62x fixed-point CPU and the C67x floating-point CPU are described. A summary of the C62x benchmark performance is also presented. The chip-level support outside the CPU that allows the C6201 to operate in a variety of high-performance DSP environments is also described. An overview of the C6x development environment is also given, demonstrating the breadth of the development environment and illustrating the programming methodology. The article concludes with a performance analysis of the C compiler View full abstract»

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IEEE Signal Processing Magazine publishes tutorial-style articles on signal processing research and applications, as well as columns and forums on issues of interest.

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University of Maryland, College Park
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