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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 1 • Date Jan. 1998

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Displaying Results 1 - 19 of 19
  • In Memoriam - Sidney Darlington (July 18, 1906-October 31, 1997)

    Publication Year: 1998 , Page(s): 1 - 2
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    Freely Available from IEEE
  • Maximum and minimum tracking performances of adaptive filtering algorithms over target weight cross correlations

    Publication Year: 1998 , Page(s): 123 - 132
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    This paper is concerned with studying the dependence of the tracking performance of the LMS, RLS, sign, signed regressor, and sign-sign algorithms on the cross correlations among the fluctuations of individual target weights. In practical applications, these cross correlations are usually unknown. Therefore, it is useful for design purposes to find the extreme values of the performance measures over all possible cross correlations. The paper derives, for each one of the above five algorithms, the conditions of target weight cross correlations that maximize and the ones that minimize the steady-state excess mean-square error ξ and the steady-state mean-square weight misalignment η. The relationship between the step sizes μξ and μη that minimize ξ and η, respectively, for given target weight cross correlations is studied. Maxima and minima of μξ and μη over all target weight cross correlations are found. The necessary and sufficient condition of equality of μξ and μη for all target weight cross correlations is derived. A rule that maps the tracking performance measures of the LMS algorithm to the ones of the RLS algorithm is found. The necessary and sufficient condition of equality of the tracking capabilities of the RLS and LMS algorithms for all target weight cross correlations is derived. A measure of the degree of ambiguity of the tracking performance, due to ignorance of target weight cross correlations, is defined. It is found that all of the above algorithms share the same degree of ambiguity, and that this degree increases with the eigenvalue spread of the input covariance matrix View full abstract»

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  • Rail-to-rail multiple-input min/max circuit

    Publication Year: 1998 , Page(s): 137 - 140
    Cited by:  Papers (19)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (96 KB)  

    The author presents a multiple-input min/max circuit technique that reduces the errors associated with previous analog implementations by combining a common-source voltage-mode configuration with a current-mode “winner takes all” circuit. The overall architecture exhibits linear complexity with the number of inputs. Both minimum and maximum two-input prototypes have been designed and built in a 2-μm CMOS process. The active area for each circuit is 650×100 μm2, and the total power dissipation is 0.8 mW from a single 5-V supply. Experimental results confirm rail-to-rail operation and sharp transition regions View full abstract»

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  • The differential difference operational floating amplifier: a new block for analog signal processing in MOS technology

    Publication Year: 1998 , Page(s): 148 - 158
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    A wide-range differential difference operational floating amplifier (DDOFA) is introduced. The DDOFA is a new block useful for continuous-time analog signal processing. The DDOFA is realized using a differential difference transconductor with large signal handling capability and a single input differential output current op-amp. The DDOFA forces two differential voltages to the same value and provides two balanced output currents. This brief presents a CMOS realization of the DDOFA, and some of its applications are provided, such as a voltage-to-current converter, MOS-grounded and floating resistors, a MOS multiplier/divider cell, a differential integrator, a continuous-time MOS-C filter, a MOS-C current oscillator, and a MOS-C floating inductor. Simulation results for the DDOFA circuit and its applications are given View full abstract»

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  • An arithmetic free parallel mixed-radix conversion algorithm

    Publication Year: 1998 , Page(s): 158 - 162
    Cited by:  Papers (4)
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    A new, parallel mixed-radix (MR) conversion algorithm, based upon lookup tables, with no required arithmetic is presented. When pipelined, an effective conversion rate of one conversion per table lookup is achieved. The new algorithm is attractive for hardware implementation since it requires no arithmetic or logical units. The algorithm is shown to be faster than existing pipelined algorithms View full abstract»

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  • Moment-based techniques for RLC clock tree construction

    Publication Year: 1998 , Page(s): 69 - 79
    Cited by:  Papers (1)  |  Patents (1)
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    While designing interconnect for MCMs, one must take into consideration the distributed RLC effects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCMs. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for buffer insertion to satisfy constraints on the clock signal slew rate. Experimental results, verified by SPICE simulations, show that this method can be used to build clock trees with near-zero skews. Computational efficiency along with its accuracy make this method ideal for computer-aided design (CAD) of RLC clock trees View full abstract»

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  • An interpolated frequency-hopping spread-spectrum transceiver

    Publication Year: 1998 , Page(s): 3 - 12
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    A technique of spread-spectrum transmission, interpolated frequency-hopping (IFH), is presented. IFH employs a carrier that moves smoothly and continuously in frequency, helping to alleviate problems, such as spectral splatter and transient mismatch, which are a concern in conventional phase-locked loop (PLL)-based frequency-hopping spread-spectrum systems. In IFH, the pseudorandom hopping code is passed through a digital interpolation filter prior to controlling the synthesizer instantaneous frequency output. While such filtering is commonly used in data pulse-shaping to improve the spectral characteristics of the modulated carrier, such filtering has not been reported for IFH codes, where the frequency deviations are changing and can span several MHz. The implications of matching the transient responses of two PLL-based frequency synthesizers using this method have also not been reported. Initial simulation and laboratory measurements indicate that, for certain cases, IFH shows a 1.9 dB improvement in received IF power, has a much sharper roll-off of inband phase noise when compared to conventional hopping, and provides a phase-coherent IF after despreading. An IFH transceiver system using Δ-Σ frequency synthesis and a Δ-Σ frequency discriminator is proposed. The system would be suitable for integrated mobile radio applications in slow-fading environments View full abstract»

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  • Spectral characteristics of the double-loop sigma-delta modulator

    Publication Year: 1998 , Page(s): 144 - 147
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    An important factor affecting the performance of ΣΔ modulators is their tone behavior. A recent approach to alleviate the tone problem consists of moving the open-loop poles outside the unit circle. In this paper, we determine the frequency location of two dominant tones as a function of pole-location, and discuss the effect of pole location on the relative amplitude of low-frequency tones. Audio testing along with a series of simulations are then performed to compare the efficacy of pole placement with that of the more traditional tone removal technique of dithering View full abstract»

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  • Hardware design of a 2-D motion estimation system based on the Hough transform

    Publication Year: 1998 , Page(s): 80 - 95
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    A novel feature-domain two-dimensional (2-D) motion estimation system based on the straight-line Hough transform (SLHT) is presented. This system implements the motion estimation technique proposed in an earlier work that represents objects uniquely by straight-line approximations of the boundary {(θ, p)} and estimates the motion parameters from shifts in the θ-p space. It operates on 256×256 pixel binary images and consists of two main blocks. The first block does preprocessing work including smoothening the boundary, tracing and integrating the contours, and detecting dominant points. The second block computes the Hough transform on contour segments as well as the rotation and translation parameters. Each of the modules has been implemented (gate level) and simulated using Mentor Graphics tools. Finally, the experimental results have been presented and compared with the results of the software implementation View full abstract»

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  • Delta operator realizations of direct-form IIR filters

    Publication Year: 1998 , Page(s): 41 - 52
    Cited by:  Papers (28)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    The use of the delta operator in the realizations of digital filters has recently gained interest due to its good finite-word-length performance under fast sampling. We studied efficient direct form structures, and show that only some of them can be used in delta configurations, while others are evidently unstable. In this paper, we focus on the roundoff noise analysis. Of all the direct-form structures, the direct form II transposed (DFIIt) delta structure has the lowest quantization noise level at its output. This structure outperforms both the conventional direct-form (delay) structures, as well as the state-space structures for narrow-band low-pass filters with respect to output roundoff noise. Excellent roundoff noise performance is achieved at the cost of only a minor additional implementation complexity when compared with the corresponding delay realization. Complexity of a signal processor implementation of the DFIIt delta structure, which was found to be the most suitable delta structure for signal processors, is compared with those of the direct form and state-space delay structures. In addition, some hardware implementation aspects are discussed, including the minimization of the internal word length View full abstract»

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  • Maximally flat low-pass FIR filters with reduced delay

    Publication Year: 1998 , Page(s): 53 - 68
    Cited by:  Papers (21)
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    This paper describes a new class of nonsymmetric maximally flat low-pass finite impulse response (FIR) filters. By subjecting the magnitude and group delay responses (individually) to differing numbers of flatness constraints, the new filters are obtained. It is found that these filters achieve a smaller delay than symmetric filters while maintaining relatively constant group delay around ω=0, with no degradation of the frequency response magnitude. The design of these filters is initially investigated using Grubner bases. An analytic design technique, applicable to a subset of the forgoing filters, is provided that does not depend on Grubner basis computations View full abstract»

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  • A low-complexity dynamic element matching DAC for direct digital synthesis

    Publication Year: 1998 , Page(s): 13 - 27
    Cited by:  Papers (23)  |  Patents (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    This paper presents and analyzes a new dynamic element matching technique for low-harmonic distortion digital-to-analog conversion. The benefit of this technique over the prior art is a significantly reduced hardware complexity with no reduction in performance. It is particularly appropriate for applications such as direct digital synthesis (DDS) in wireless communications systems, where low hardware complexity and low harmonic distortion are essential View full abstract»

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  • Chebyshev optimization for the design of broadband beamformers in the near field

    Publication Year: 1998 , Page(s): 141 - 143
    Cited by:  Papers (26)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    The use of microphone arrays for video conferences, hands-free mobile telephony and computer applications has created the demand for near-field broadband beamformer design methods. Here, a general broadband beamformer design problem is formulated as a weighted Chebyshev optimization problem, and a method to solve the resulting functionally-constrained problem is presented. The formulation can also be applied to the design of multidimensional digital finite-impulse response (FIR) filters with an arbitrarily specified amplitude and phase. Numerical results that demonstrate the minimax near-field behavior of the designed beamformers are given View full abstract»

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  • A VLSI architecture for arithmetic coding of multilevel images

    Publication Year: 1998 , Page(s): 163 - 168
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    We describe a VLSI architecture of an arithmetic coder for a multilevel alphabet (256 symbols) that includes the storing and updating of probabilities, the updating of the interval, and the correction of the codeword. The architecture is based on the utilization of redundant arithmetic, and the development of new schemes for storing and updating the cumulative probabilities and updating the range and left point of the current interval. The proposed implementation is compared with one that does not include these improvements, and is shown to result in a significantly lower complexity and shorter cycle View full abstract»

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  • Realization of the CMOS pulsewidth-modulation (PWM) neural network with on-chip learning

    Publication Year: 1998 , Page(s): 96 - 107
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    In this paper, a CMOS very large scale integration (VLSI) design of the pulsewidth-modulation (PWM) neural network with both retrieving and on-chip leaning functions is proposed. In the developed PWM neural system, the input and output signals of the neural network are represented by PWM signals whereas the multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Therefore, the designed neural network only occupies the small chip area. After compensating the nonideal effects of the switches, the designed circuits have good linearity and large dynamic range. This makes the implementation of onchip learning feasible. To demonstrate the learning capability of the realized PWM neural network, the delta learning rule is realized. An experimental chip with two neurons, twelve synapses, and the associated learning circuits has been fabricated in 0.8 μm CMOS double-poly double-metal process. The chip area, including the pads, is 3.45 mm×3.45 mm. From the measured results, the linearity of synapses versus weight voltages and input pulsewidths can almost be kept under ±1% and ±0.2%, respectively. The measured results on the three learning examples on AND function, OR function, and simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network View full abstract»

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  • A new blind equalization structure for deep-null communication channels

    Publication Year: 1998 , Page(s): 108 - 114
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB)  

    We propose a new blind equalization structure that is well suited for communication channels characterized by deep spectral nulls and that directly estimates the channel coefficients. Blind equalization of communication channels has increasing importance, due to the need to maximize bandwidth efficiency. Established Bussgang algorithms applied to finite impulse response (FIR) structure equalizers perform poorly when one or more maximum phase zero of the channel is close to the unit circle. This limitation is due to the difficulty of modeling the inverse of the maximum phase component of the channel with a finite length FIR filter. Theoretical analysis and simulation studies support the potential of the new structure to model the required inverse entirely and, hence, to equalize such difficult channels View full abstract»

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  • Tracking analysis of the sign algorithm without the Gaussian constraint

    Publication Year: 1998 , Page(s): 115 - 122
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    This paper is concerned with the analysis of the sign algorithm (SA) when used to adapt a finite impulse response (FIR) filter with randomly time-varying target weights. The analysis is done under the assumption that positive and negative polarities of the noise are equally probable and that the noise probability density function at the origin exists and is strictly positive, This assumption fits many noise distributions encountered in applications. Expressions of the excess mean square error ξ and the mean square weight misalignment η are derived. It is found that both ξ and η are independent of the type of distribution of the filter input. Both ξ and η are proportional to the reciprocal of the noise probability density function at the origin. The step sizes that minimize ξ and η are found to be independent of both the variance and the type of distribution of the noise. Given the sum of the mean square target weight fluctuations, it is found that ξ (resp. η) is independent (resp. dependent) on both the mean squares of individual target weight fluctuations and the mutual correlation among them. The tracking properties of the SA are found to be strongly related to the ones of the LMS algorithm. It is shown that the charts of ξ and η versus the step size of the SA can be obtained from the corresponding ones of the LMS algorithm via a simple linear transformation that depends only on the noise distribution. The above results hold for both continuous and discrete distributions of the input of the filter View full abstract»

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  • A built-in current sensor based on current-mode design

    Publication Year: 1998 , Page(s): 133 - 137
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    A very simple yet powerful design of a built-in current sensor for CMOS IDDQ testing is presented. Compared with previous methods, this design has lower sensitivity to parameter deviation caused by process or temperature variations. In addition, this design provides scalable sensing resolutions and programmable current reference. Experimental results show that a test response time of less than 2 ns can be acquired when the faulty IDDQ current is higher than 250 μA View full abstract»

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  • Design techniques for 1.5-V low-power CMOS current-mode cyclic analog-to-digital converters

    Publication Year: 1998 , Page(s): 28 - 40
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    Design techniques to realize low-voltage low-power (LVLP) cyclic current-mode analog-to-digital converters (IADCs) in the CMOS digital process are presented. First, a modified reference-nonrestoring (MRN) algorithm is proposed. By using the MRN algorithm, the digital correction (DCN) technique ran be embedded into the cyclic architecture to reduce the linearity errors caused by the comparator inaccuracy and the offset of the sample/hold (S/H) operations. Moreover, new LVLP fully differential current-mode circuits performing the S/H, multiplication-by-2, and current comparison are also developed to implement the cyclic IADC without the use of linear capacitors or a multithreshold process. An experimental chip for the proposed IADC with an active area of 4 mm2 has been fabricated in 0.8 μm n-well CMOS technology. With a 1.5 V supply voltage, the fabricated IADC achieves 10 bit resolution with the differential nonlinearity (DNL) of 0.63 LSB and integral nonlinearity (INL) of 1.4 LSB when operated at a 12 ks/s conversion rate. The power consumption of the IADC core circuit is 2 mW View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope