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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 4 • Date April 1997

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Displaying Results 1 - 12 of 12
  • Corrections to "Wideband Cmos Transconductor for Analog Vlsi Systems"

    Publication Year: 1997 , Page(s): 338
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (21 KB)  

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  • Optimal design of partial-band time-varying systems

    Publication Year: 1997 , Page(s): 274 - 283
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    The design of partial-band linear periodically time-varying systems (PBTV) imitating linear time-invariant (LTI) systems is approached using a relative t2 error criterion. This error criterion results from a natural extension of the Chebyshev error criterion for the design of LTI systems. A complete analysis of the error criterion is presented. An algorithm is introduced which finds a locally optimal solution. This algorithm is based on recent results in nonsmooth optimization. The methods introduced allow the designer to compare as well as design PBTV systems in a systematic and meaningful manner View full abstract»

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  • A VLSI design methodology for RNS full adder-based inner product architectures

    Publication Year: 1997 , Page(s): 315 - 318
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    In this paper, a systematic graph-based methodology for synthesizing VLSI RNS architectures using full adders as the basic building block is introduced. The design methodology derives array architectures starting from the algorithm level and ending up with the bit-level design. Using as target architectural style the regular array processor, the proposed procedure constructs the two-dimensional (2-D) dependence graph of the bit-level algorithm, which is formally described by sets of uniform recurrent equations. The main characteristic of the proposed architectures is that they can operate at very high-throughput rates. The proposed architectures exhibit significantly reduced complexity over ROM-based ones View full abstract»

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  • LBR realization of MIMO systems using rotation blocks

    Publication Year: 1997 , Page(s): 310 - 315
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    This paper introduces a lossless bounded real (LBR) realization method of multi-input multi-output (MIMO) systems using rotation blocks. For this, it first discusses how to realize a given LBR system in the form of LBR two-pair cascades, and then it examines a systematic extraction procedure which enables realization of each LBR two-pair in the form of rotation block. Finally, it demonstrates the LBR realization method using a detailed numerical example: a given HR transfer function is first converted into a 4×4 TDF transfer matrix, which is then realized in a rotation block cascade View full abstract»

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  • Generation of current conveyor-based all-pass filters from op amp-based circuits

    Publication Year: 1997 , Page(s): 324 - 330
    Cited by:  Papers (56)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    It is shown that two of the recently reported voltage mode and current mode current conveyor-based all-pass circuits can be generated from the well known single input op amp all-pass configuration. It is also found that two other voltage mode current conveyor-based all-pass circuits are related directly to the differential input op amp all-pass structure. Several new grounded capacitor all-pass circuits are introduced. A new universal biquad circuit which realizes complex poles and employs a single current conveyor is also given. PSpice simulation results are included View full abstract»

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  • Behaviour of stability tests for two-dimensional digital recursive filters when faced with rounding errors

    Publication Year: 1997 , Page(s): 319 - 323
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    In this paper, the behaviour of four recent algorithms, which test the stability of two-dimensional (2-D) real recursive filters, are compared when faced with rounding errors in floating point arithmetic. Experimental results, comparing the data given by these algorithms when they are implemented either in floating point arithmetic, or with infinite precision in formal calculus, are presented. It appears with this comparison, that this behaviour is a very important point for choosing such an algorithm among all the existing ones View full abstract»

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  • Offset current cancellation based on a multiple-path feedback compensation (MPFC) technique for switched-current circuits and systems

    Publication Year: 1997 , Page(s): 299 - 309
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    This paper presents a new offset current cancellation technique called multiple-path feedback compensation (MPFC) for greatly reducing offset currents at both output and internal nodes of SI circuits and systems. In order to analyze the effects and the statistical distribution of DC current offsets of large SI systems, a very simple and efficient SI model is first used. This model can be used for fast, accurate, statistical, and systematic analyzes of system characteristics such as offset current, frequency response, stability, scaling, and sensitivity. Based on the model, a complex SI system can be transferred to a simple signal flow graph, which can be represented by linear state equations. From the state equations, statistical Monte Carlo simulation is used to obtain optimal MPFC coefficients. A fifth-order Chebyshev SI filter is illustrated as an example for implementation and verification of the proposed MPFC technique. Ninety test chips have been fabricated with a 1-μm CMOS n-well digital process. Increased percentages of circuit area and power consumption due to the use of the MPFC circuit are 5% and 4%, respectively. Measured results show that the variance of output offset currents is reduced to 2% of its original amount. Besides, the peak signal-to-noise ratio (PSNR) is increased by 3 dB and the total harmonic distortion is reduced by 10 dB View full abstract»

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  • Design of an array processor for parallel skeletonization of images

    Publication Year: 1997 , Page(s): 284 - 298
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    This paper presents the design, evaluation, and the implementation of an application specific array processor (ASAP) desirable for high speed parallel skeletonization of binary images. The array processor receives the input image in a binary form and generates the skeleton of the nonzero regions (objects, or silhouettes) contained in the image in parallel. In particular, each processing element (PE) of the array processor receives additional information from the neighboring PE's and executes independently its own algorithm by maintaining or zeroing its own value “1” for the final generation of the skeleton of the object, The skeletons produced by this array processor are: (1) region's size independent (nonsensitive in small variation of shape) and (2) sensitive to the region's shape. The ability of the array processor to produce these two types of skeleton makes it flexible for image processing applications such as handwritten character recognition under uncertainty (non sensitive skeleton), or detection of defects on printing circuits (sensitive skeleton). A comparison of the proposed algorithm [parallel symmetric thinning algorithm (PSTA)] to a number of other parallel thinning algorithms is also provided indicating its advantages and disadvantages View full abstract»

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  • Further simplification to 2-D filter stability test

    Publication Year: 1997 , Page(s): 330 - 332
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB)  

    A further simplification to the stability test of the characteristic polynomial D(x1,x2) of a two-dimensional (2-D) filter is achieved by the following two modifications in the test procedure. At first, the modified Jury table is used to construct the polynomial array and then the real form of Siljak's theorem applied. Secondly, the positivity test on Δn , the last entry of the polynomial array, is further reduced to tests on its factors D(x1,1), D(x1,-1) and Δ Δn-1-(x1), which are of much lower orders in x1 View full abstract»

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  • A differential active load and its applications in CMOS analog circuit designs

    Publication Year: 1997 , Page(s): 265 - 273
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    In this paper we describe a CMOS differential active load and show how it can be used to create various useful structures. Tunable current gain stages and current squaring circuits are discussed. Their connection to a differential pair-based transconductor results in broad-range tunable transconductor structures suitable for adaptive continuous-time filtering applications and a four-quadrant voltage multiplier View full abstract»

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  • On numerical technique in analog filter synthesis

    Publication Year: 1997 , Page(s): 336 - 338
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (60 KB)  

    After a brief review of the accuracy problem found in filter synthesis, we describe a computer program designed to measure the precision of the product method in the s-plane (i.e. without using transformed variables). This is found to give 15 digit precision for all degrees, with possibly several units off in the least significant digit. The tests were done in double precision up to degree 60 View full abstract»

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  • An efficient implementation of forward-backward LMS adaptive filters

    Publication Year: 1997 , Page(s): 332 - 336
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    Without changing the characteristics of the forward-backward LMS (FBLMS) adaptive line enhancer, an efficient implementation of FBLMS adaptive filters is presented in this paper. This implementation technique reduces 25% of multiplications and 12.5% of additions in two successive time samples in comparison to that of the direct implementation of the FBLMS algorithm in both prediction and weight control sections View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope