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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 10 • Date Oct 1996

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Displaying Results 1 - 6 of 6
  • Subexpression sharing in filters using canonic signed digit multipliers

    Publication Year: 1996 , Page(s): 677 - 688
    Cited by:  Papers (220)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB)  

    A common way of implementing constant multiplication is by a series of shift and add operations. As is well known, if the multiplier is represented in Canonical Signed Digit (CSD) form, then the number of additions (or subtractions) used will be a minimum. This paper examines methods for optimizing the design of CSD multipliers, and in particular the gains that can be made by sharing subexpressions. In the case where several multipliers are present in a network of operators, for instance in an FIR filter, the savings achieved by identifying common subexpressions can be as much as 50% of the total number of operators. The asymptotic frequency of the most common subexpression is analyzed mathematically, and it is shown that sharing the two most common subexpressions can be expected to lead to a 33% saving of the number of additions View full abstract»

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  • Analog fault diagnosis based on ramping power supply current signature clusters

    Publication Year: 1996 , Page(s): 703 - 712
    Cited by:  Papers (23)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (924 KB)  

    Measurement of power supply currents was found to be very useful for testing CMOS IC's because of its potential to detect a large class of manufacturing defects. However, this technique was used mainly for fault detection and was confined to digital circuits. In this paper, we present a suited methodology for fault diagnosis of analog circuits based on the observation of power supply currents. In the proposed technique, fault signature dictionaries are generated from the currents in the power supply bus. To obtain signatures rich in information for efficient diagnosis, the transistors in the circuit are forced to operate in all possible regions of operation by using a ramp signal at the supply instead of the conventional constant DC signal or ground voltage. The signatures are then clustered into different groups using a Kohonen neural network classifier. This technique has the potential to detect and diagnose single and multiple shorts as well as open circuits. The theoretical and experimental results of the proposed technique are verified using a CMOS Operational Transconductance Amplifier (OTA) circuit View full abstract»

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  • Unlearning algorithm in associative memory

    Publication Year: 1996 , Page(s): 723 - 729
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    We incorporate into a synthesis procedure for a class of discrete-time neural networks an unlearning capability. The proposed technique increases storage capacity while maximizing the domain of attraction of each desired pattern to be stored. Making use of learning and forgetting capabilities, neural networks generated by the method advanced herein are capable of learning new patterns as well as forgetting learned patterns without the necessity of recomputing the entire interconnection weights and external inputs. The unlearning algorithm developed is then utilized off-line to equalize the basins of attraction for each desired pattern to be stored, and to minimize the number of spurious states. Specific examples are given to illustrate the strengths and weaknesses of the methodology advocated herein View full abstract»

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  • A zero-delay FFT-based subband acoustic echo canceller for teleconferencing and hands-free telephone systems

    Publication Year: 1996 , Page(s): 713 - 717
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    A new structure of the subband acoustic echo canceller (AEC) is proposed. It introduces no delay in the transmission line. Using the new structure and a simplified weighted overlap-add method, an acoustic echo canceller is designed. The results showed that the designed system has good echo reduction and is stable in nonstationary environments. A hardware implementation of the proposed subband AEC is also presented in this brief View full abstract»

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  • Area-time-power tradeoffs in parallel adders

    Publication Year: 1996 , Page(s): 689 - 702
    Cited by:  Papers (59)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1044 KB)  

    In this paper, several classes of parallel, synchronous adders are surveyed based on their power, delay and area characteristics. The adders studied include the linear time ripple carry and Manchester carry chain adders, the square-root time carry skip and carry select adders, the logarithmic time carry lookahead adder and its variations, and the constant time signed-digit and carry-save adders. Most of the research in the last few decades has concentrated on reducing the delay of addition. With the rising popularity of portable computers, however, the emphasis is on both high speed and low power operation. In this paper we adopt a uniform static CMOS layout methodology whereby short circuit power mininization is used as the optimization criterion. The relative merits of the different adders are evaluated by performing a detailed transistor-level simulation of the adders using HSPICE. Among the two's complement adders, a variation of the carry lookahead adder, called ELM, was found to have the best power-delay product. Based on the results of our experiments, a large adder design space is formulated from which an architect can choose an adder with the desired characteristics View full abstract»

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  • Implementation of the FFT butterfly with redundant arithmetic

    Publication Year: 1996 , Page(s): 717 - 723
    Cited by:  Papers (9)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    We present an architecture for the implementation of the radix-4 FFT butterfly with redundant arithmetic, based on the utilization of carry-save adders and a signed-digit representation of the multipliers in the multiplications. As the carry propagation is eliminated, a high throughput is maintained with a reduced hardware cost when compared to other architectures based on carry-propagate additions View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope