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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Issue 11 • Date Nov. 1995

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Displaying Results 1 - 19 of 19
  • Guest Editorial

    Publication Year: 1995
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    Freely Available from IEEE
  • Design considerations on low-voltage low-power data converters

    Publication Year: 1995 , Page(s): 853 - 863
    Cited by:  Papers (22)  |  Patents (2)
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    In this paper, we discuss theoretical and practical issues concerning low-voltage and low-power data converters. By looking at a series of constraints affecting the design of basic elements and building blocks, the paper analyzes different architectures for Nyquist rate data converters and discusses important aspects of low-voltage and low-power operation. Following this, the minimization of power consumption in the very popular sigma-delta technique is considered. A number of hints and indications are provided throughout the paper View full abstract»

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  • Low-voltage CMOS analog circuits

    Publication Year: 1995 , Page(s): 864 - 872
    Cited by:  Papers (7)  |  Patents (5)
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    This paper addresses the issue of low-voltage analog circuit design in CMOS technology. In particular, three areas of design are discussed: switched-capacitor circuits, continuous-time circuits for low-frequency applications, and RF circuits. For each category examples are given together with measured data View full abstract»

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  • Charge sharing problems in dynamic logic circuits: BiCMOS versus CMOS and a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems

    Publication Year: 1995 , Page(s): 974 - 977
    Cited by:  Papers (4)
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    This brief reports comparison of the charge sharing problems between BiCMOS and the CMOS dynamic logic circuits for both 5 V and 1.5 V operations. In addition, a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems is reported. Based on the analysis, the 1.5 V full-swing BiCMOS dynamic logic gate circuit without charge sharing problems shows a more than 1.5 times improvement in speed as compared to the CMOS one View full abstract»

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  • Low-power low-voltage VLSI operational amplifier cells

    Publication Year: 1995 , Page(s): 841 - 852
    Cited by:  Papers (39)  |  Patents (16)
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    VLSI operational amplifier cells that approach the physical limitations of bandwidth, gain, and power consumption are described. To this purpose, several HF compensation architectures are presented, such as parallel Miller, multipath nested Miller, and multipath hybrid nested Miller View full abstract»

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  • Low-voltage analog filters

    Publication Year: 1995 , Page(s): 827 - 840
    Cited by:  Papers (53)  |  Patents (1)
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    This paper reviews the design of analog filters at low supply voltage. In particular, the main focus is on switched capacitor and g m-C type filters because, at the present time, they have the greatest commercial importance. SC implementations are discussed in the context of low frequency high precision applications while gm-C implementations are discussed in the context of high frequency medium/low precision applications. Both fundamental and practical limitations to the achievable dynamic range at low supply voltage are explained. The paper reviews well established circuit and architectural techniques as well as some promising new ones that might result in performance improvements in the future View full abstract»

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  • A design framework for low power analog filter banks

    Publication Year: 1995 , Page(s): 966 - 971
    Cited by:  Papers (18)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    We detail the design of multiresolution analog filter banks, linear models of cochlear function, with power dissipation being a prime engineering constraint. We propose that a reasonable goodness criterion is the information rate through the system, per watt of power dissipated. Speech applications requiring filter banks with a wide frequency tuning range, from 20 Hz to 20 kHz, and low power consumption make the transconductance-C integrator in subthreshold CMOS the preferable integrator structure. As an example, the dynamic range of a lowpass filter is computed and subsequently used to design a filter bank that models faithfully cochlear micro-mechanics. The power consumption of the entire filter bank is computed from analytical expressions and is estimated as 355 nW, at 68 kb/s overall information rate at the output of the system View full abstract»

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  • Universal constant-gm input-stage architectures for low-voltage op amps

    Publication Year: 1995 , Page(s): 886 - 895
    Cited by:  Papers (38)  |  Patents (2)
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    In this paper, a novel design technique for low-voltage, constant transconductance (gm) op amp input stages is presented. The new technique which uses current-mode circuits is based on processing signal currents, rather than handling DC tail currents, to achieve a constant-gm. Two cases are developed. One is based on processing signal currents (the AC case) while the other is based on processing total instantaneous currents (the TIC case). The adopted design strategy in both cases is universal in that it is independent of the input stage transistor types (FET or bipolar) and their operating regions. It also considerably simplifies the design procedure of low-voltage op amps. To demonstrate the new concepts, universal op amp input stage architectures have been developed and their performances have been verified in both MOS and bipolar design examples. The MOS designs have been verified in both weak and strong inversion. The proposed universal implementations achieve almost constant-gm, independent of the common mode input voltage range from rail-to-rail View full abstract»

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  • A low-voltage low-power fully-integratable front-end for hearing instruments

    Publication Year: 1995 , Page(s): 920 - 932
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB)  

    The front-end of a universally applicable analog integrated circuit for hearing instruments is presented. This IC comprises the following functions: a microphone preamplifier, a pickup-coil preamplifler, a second-order high-pass filter and a second-order low-pass filter, both with a controllable cutoff frequency, and an input-controlled automatic gain control with an adjustable knee level. By applying a compression/expansion system and operating all the circuits in the current domain as much as possible, all these functions can be implemented in a single IC, without the need for external components. The test chip demonstrates operation down to 1.05 V and a current consumption between 120 and 175 μA. The full-custom chip area in a 2.5-μm BiCMOS process (using only vertical NPN's and lateral PNP's) amounts to 2.4 mm2 View full abstract»

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  • A 3 V 12-55 MHz BiCMOS pseudo-differential continuous-time filter

    Publication Year: 1995 , Page(s): 896 - 903
    Cited by:  Papers (39)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB)  

    The reduction of the supply voltage forces one to develop system and circuit solutions able to achieve the same performance previously obtained with higher supply voltage. In this paper, a second-order low-pass continuous-time filter operating at a 3 V power supply is presented. The prototype filter is implemented using a highly linear pseudo-differential transconductor. The input common-mode signal is canceled at the transconductor level using a feed-forward path. The output common mode voltage is controlled at the filter level using lossy integrators. A prototype cell has been realized in 1.2 μm BiCMOS technology. The pole frequency can be tuned in the range 12-55 MHz. A THD of -40 dB is achieved for signals up to 1 Vpp at 10 MHz. The dynamic range is approximately 60 dB View full abstract»

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  • A pulse stream system for low-power neuro-fuzzy computation

    Publication Year: 1995 , Page(s): 946 - 954
    Cited by:  Papers (15)
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    This paper describes a VLSI device designed for low-power Neuro-Fuzzy computation, which is based on Coherent Pulse Width Modulation. The device implements several Neural and Fuzzy paradigms. Weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit. The performance of the system is analyzed theoretically, and results are compared against values measured from a prototype device, which contains a 32×32 synaptic array, consuming 10 mW of power at 140 MCPS View full abstract»

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  • Application of the back gate in MOS weak inversion translinear circuits

    Publication Year: 1995 , Page(s): 958 - 962
    Cited by:  Papers (15)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    Though the MOS transistor is a four-terminal device, it is most often used as a three-terminal device. Therefore, a large number of possible MOS circuits are overlooked. In this brief, the four-terminal point of view is elaborated with respect to MOS weak inversion translinear circuits, a class of circuits naturally very suitable for low-voltage and low-power applications. Some new circuits are described which sometimes are more suitable for low-voltage applications than bipolar translinear networks performing the same function. It is also shown that, using the back gate, translinear networks can be derived which cannot be realized with bipolar transistors. These network topologies increase the possibilities offered by translinear technology. As an example, measurement results of a low input-voltage current mirror and a sin(x)-circuit are shown View full abstract»

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  • Low-voltage circuits building blocks using multiple-input floating-gate transistors

    Publication Year: 1995 , Page(s): 971 - 974
    Cited by:  Papers (52)  |  Patents (1)
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    A systematic approach for designing analog circuits with low supply voltage requirements is discussed. This approach is based on the utilization of multiple-input floating-gate transistors. Current mirrors and differential pair building blocks are discussed as well as a low voltage BiCMOS operational amplifier based on these building blocks View full abstract»

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  • A very low frequency, micropower, low voltage CMOS oscillator for noncardiac pacemakers

    Publication Year: 1995 , Page(s): 962 - 966
    Cited by:  Papers (11)
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    One of the most power consuming components of a modern noncardiac pacemaker is the oscillator circuitry. This brief details the design of a micropower, low voltage, low frequency oscillator consisting of CMOS devices operating in subthreshold. Since the frequency of a typical oscillator is proportional to Current/Capacitance, the operation of the transistors in the subthreshold region allows the size of the capacitance to be reduced significantly in addition to decreasing the quiescent power consumption. The proposed prototype oscillator was fabricated in a 2 μm n-well CMOS process and occupies 0.281 mm2 including a 100 pf capacitor which takes 77.8% (0.219 mm2 ) of the total area. Experimental results show a frequency of oscillation as low as 0.3 Hz and a power consumption of around 0.24 μW at 0.3 Hz to 0.3 μW at 100 Hz with a 2 V supply voltage View full abstract»

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  • A micropower CMOS algorithmic A/D/A converter

    Publication Year: 1995 , Page(s): 913 - 919
    Cited by:  Papers (10)  |  Patents (1)
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    A low-power and compact VLSI architecture, implementing a bidirectional bit-serial A/D/A (analog-to-digital and digital-to-analog) converter, is presented. Both functions of algorithmic D/A conversion and successive approximation A/D conversion are combined into a single device, converting bits in the order from most to least significant. The MSB-first order guarantees robust implementation, relatively insensitive to component mismatches, offsets and nonlinearities. Also, since the A/D conversion makes use of the intermediate D/A conversion results, matched monotonic characteristics are obtained in both directions of conversion. The final D/A result is available at the end of A/D conversion, and can be used directly in applications calling for analog quantization. More general use of the A/D/A converter allows for bidirectional read/write digital access to local analog information in VLSI. The robust architecture supports dense integration of multiple low-power data conversion units along with digital processors or sensory circuitry in a standard CMOS process. Minimum sizing of active and passive devices in the implementation, to obtain optimal area and energy efficiency, is limited by clock feedthrough and finite gain considerations rather than matching requirements. Experimental results from a prototype VLSI implementation are given. Including control logic, the A/D/A cell measures 216 μm×315 μm in a 2-μm CMOS process, and achieves 8-b untrimmed monotonicity at 200 μW power consumption for a 20 μs conversion cycle. This corresponds to 4 nJ of energy dissipated per 8-b converted sample View full abstract»

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  • A compact low-power VLSI transceiver for wireless communication

    Publication Year: 1995 , Page(s): 933 - 945
    Cited by:  Papers (3)  |  Patents (2)
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    A 3 V CMOS VLSI for dual-mode wireless communication systems has been designed and fabricated using the MOSIS scaleable CMOS technology. By using mixed analog and digital circuit design techniques, a single chip solution to baseband processing of data and supervisory audio tone signals in the analog transmission mode is possible. Key analog circuits include an anti-alias filter, two fifth-order low-pass filters, one sixth-order band-pass filter, an interpolator for sampling rate conversion, and two comparators. The digital modules perform data transmission and reception, error coding and decoding, as well as tone detection and regeneration. When implemented in the 2 μm CMOS technology from the MOSIS Service for low-cost low-power applications, the transceiver chip consumes less than 6 mW at receive-only mode. It is also quite suitable for battery-powered devices, such as portable terminals. Design technologies can be applied to future high-speed wireless transceiver design. The architecture and circuits described in this chip can be used in aggressively scaled technologies even with the supply voltage reduced toward 1 V if the threshold voltage is proportionally decreased View full abstract»

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  • Low-voltage analog IC design in CMOS technology

    Publication Year: 1995 , Page(s): 955 - 958
    Cited by:  Papers (11)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    In this brief, various problems confronting analog designers due to low supply voltage requirements are investigated. Some of the limiting factors are determined, and new solutions for low voltage design are proposed and demonstrated in two different circuits, namely a linear four quadrant analog multiplier and a rail-to-rail constant-gm input stage. The circuits were fabricated in a p-well 2 μm CMOS process available through MOSIS View full abstract»

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  • A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS

    Publication Year: 1995 , Page(s): 904 - 912
    Cited by:  Papers (21)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    An analog-to-digital converter (ADC) circuit is proposed that utilizes the linearity of the single-bit first-order sigma-delta in a first mode technique. In a second mode, successive approximation is used to convert the remaining voltage from the first conversion to increase the resolution without significantly increasing the conversion time. Both operations can be made in the same hardware, and only a counter is needed as decimation filter so that the converter becomes both area and power efficient. A channel of the ADC implemented in standard CMOS occupies an area of 40×1640 μm2. The control logic and reference voltage generation circuits, common for the ADC array, occupy a similar area. Estimated power consumption per ADC channel is about 0.5 mW including reference voltage generation. The conversion speed per ADC channel is 12.8 ksamples/s at a clock rate of 3.4 MHz. The ADC concept is suitable whenever a high resolution at a moderate speed is needed View full abstract»

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  • Circuit design techniques for very low-voltage analog functional blocks using triple-tail cells

    Publication Year: 1995 , Page(s): 873 - 885
    Cited by:  Papers (9)  |  Patents (2)
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    Novel circuit design techniques for very low-voltage analog functional blocks using triple-tail cells are presented. A triple-tail cell is operable on very low voltage because it possesses a very simple circuit structure, and it operates as a gain controllable differential amplifier and a tunable rectifier. It is very suitable for analog functional blocks, such as operational transconductance amplifiers (OTA's), four-quadrant analog multipliers, logarithmic intermediate-frequency (IF) amplifiers, and automatic gain control (AGC) amplifiers, to be realized using triple-tail cells with a small circuit scale. Therefore, a triple-tail cell is the most essential circuit for very low-voltage operation in signal processing. Furthermore, very low-voltage operation at a 1 V supply voltage and the fundamental characteristics of the basic circuits consisting of triple-tail cells, such a transconductance controllable OTA, four-quadrant analog multipliers, a logarithmic IF amplifier, and an AGC amplifier, were verified with transistor-arrays and discrete components on a breadboard View full abstract»

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