# IEEE Journal of Solid-State Circuits

## Filter Results

Displaying Results 1 - 25 of 32

Publication Year: 2019, Page(s):C1 - C4
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• ### IEEE JOURNAL OF SOLID-STATE CIRCUITS

Publication Year: 2019, Page(s): C2
| PDF (81 KB)

Publication Year: 2019, Page(s):609 - 610
| PDF (211 KB)
• ### Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference

Publication Year: 2019, Page(s):611 - 612
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• ### An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage

Publication Year: 2019, Page(s):613 - 622
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A fully integrated CMOS temperature-to-digital converter utilizing MOSFETs in the sub-threshold region is proposed. The temperature-to-digital converter achieves the ultra-low power operation required for Internet of Things (IoT) nodes. The proposed principle takes the ratio of the sub-threshold currents of two nMOSFETs whose drain voltages are maintained well above and well below the thermal volt... View full abstract»

• ### A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing

Publication Year: 2019, Page(s):623 - 635
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This paper introduces a voltage-controlled oscillator (VCO)-based nonuniform sampling (NUS) analog-to-digital converter (ADC), which shifts the conventional voltage-domain level crossing to the phase domain, thus eliminating the need for any continuous-time (CT) comparator or reference generator. It increases the signal bandwidth and reduces the implementation costs of both analog and digital circ... View full abstract»

• ### A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter

Publication Year: 2019, Page(s):636 - 645
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This paper presents a compact 10-b successive approximation register analog-to-digital converter (SAR ADC) in 65-nm CMOS with an integrated passive finite impulse response (FIR) filter for anti-aliasing. Conventional switched-capacitor digital-to-analog converters (DACs) are usually implemented with unit elements for the best matching performance, at the cost of increased chip area. Instead, this ... View full abstract»

• ### A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers

Publication Year: 2019, Page(s):646 - 658
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Ring amplification has recently been shown capable of simultaneously achieving high linearity and high bandwidth (BW) in low-voltage, deep nanoscale CMOS processes, while retaining good power efficiency. In these processes, the low but very flat open-loop (OL) gain versus output voltage characteristic of the ring amplifier can be exploited, together with its high BW, to overcome the low intrinsic ... View full abstract»

• ### A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS

Publication Year: 2019, Page(s):659 - 671
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The emergence of four-level pulse amplitude modulation (PAM-4) standards to increase data rates motivates the use of receiver front ends that utilize high-speed analog-to-digital converters (ADCs) followed by digital signal processing (DSP) to provide robust digital equalization. This paper presents an ADC-based PAM-4 receiver employing a 32-way time-interleaved, 2-bit/stage, 6-bit successive appr... View full abstract»

• ### A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS

Publication Year: 2019, Page(s):672 - 684
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This paper presents a four-level pulse amplitude modulation (PAM4) quarter-rate receiver that efficiently compensates for moderate channel loss in a robust manner through background adaptation of the receiver thresholds and equalization taps. The front-end utilizes an input single-stage continuous-time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancellation requireme... View full abstract»

• ### A 15-Gb/s Sub-Baud-Rate Digital CDR

Publication Year: 2019, Page(s):685 - 695
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This paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, ... View full abstract»

• ### A Noise Circulating Oscillator

Publication Year: 2019, Page(s):696 - 708
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This paper presents a noise circulating crosscoupled voltage-controlled oscillator (VCO) topology with a transformer-based tank. The introduced noise circulating active core greatly suppresses the effective noise power from the active devices while offering the same amount of negative resistance compared to conventional cross-coupled VCO topologies. The mechanism of noise circulation is investigat... View full abstract»

• ### A Compact Transformer-Combined Polar/Quadrature Reconfigurable Digital Power Amplifier in 28-nm Logic LP CMOS

Publication Year: 2019, Page(s):709 - 719
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This paper presents a transformer-combined dual-mode reconfigurable digital Class-D power amplifier (PA) that supports polar and quadrature transmitters (TXs). Transformer-based load modulation is employed to enhance the efficiency in both modes. The PA is implemented in 28-nm logic LP CMOS and occupies only 0.56 mm2 active area. The polar mode achieves 28.8-dBm peak power with the PAE ... View full abstract»

• ### A Fully Integrated Li-Ion-Compatible Hybrid Four-Level DC–DC Converter in 28-nm FDSOI

Publication Year: 2019, Page(s):720 - 732
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This paper presents a Li-ion-compatible fully integrated hybrid dc–dc converter implemented in 28-nm FDSOI. A modified four-level converter is proposed to achieve high efficiency while operating from the 2.8–4.2-V Li-ion battery range by using stacked 1.5-V transistors. In this paper, the proposed driver architecture exploits the internal nodes of the power stage as power/GND rails for drivers, el... View full abstract»

• ### AC-Coupled Stacked Dual-Active-Bridge DC–DC Converter for Integrated Lithium-Ion Battery Power Delivery

Publication Year: 2019, Page(s):733 - 744
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Mobile, wearable, and Internet-of-Things (IOT) electronic systems are typically powered by a single-cell lithium-ion (Li-ion) battery. Increasing demand for battery life and the constraint of the overall platform size impose an emerging desire for an efficient and compact power conversion stage that can directly deliver power from the battery, which ranges from 3.2 to 4.2 V, to the supplies of app... View full abstract»

• ### Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories

Publication Year: 2019, Page(s):745 - 754
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Adaptive artificial neural network (ANN)coupled low-density parity-check (LDPC) error-correcting code (ECC) (ANN-LDPC ECC) is proposed to increase acceptable errors for various NAND flash memories. The proposed ANN-LDPC ECC can be the universal solutions for 3-D and 2-D, charge-trap and floating-gate NAND flash memories. In 3-D NAND flash, lateral charge migration, vertical charge de-trap, inter f... View full abstract»

• ### A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Publication Year: 2019, Page(s):755 - 767
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In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f3) and thermal (1/f2) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while c... View full abstract»

• ### Integrated Synthetic Fourth-Order $Q$ -Enhanced Bandpass Filter With High Dynamic Range, Tunable Frequency, and Fractional Bandwidth Control

Publication Year: 2019, Page(s):768 - 784
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This paper demonstrates a tunable synthetic fourth-order bandpass filter (BPF) at microwave frequencies. Two parallel second-order Q-enhanced LC BPFs responses are added with the out of phase to synthesize a fourth-order BPF response. The filter is implemented in a 130-nm SiGe BiCMOS technology with a core die area of 0.53 × 0.7 mm2. The filter center frequency can be tuned from 4 to 8 ... View full abstract»

• ### Design and Analysis of a DCO-Based Phase-Tracking RF Receiver for IoT Applications

Publication Year: 2019, Page(s):785 - 795
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This paper presents an energy-/area-efficient digitally controlled oscillator (DCO)-based phase-tracking Receiver for Internet-of-Things (IoT) applications. The RX leverages the constant-envelope nature of frequency shift keying modulation adopted in many IoT protocols, e.g., IEEE802.15.4 and Bluetooth low energy (BLE), to enhance the energy efficiency and to reduce the chip area. The proposed RX,... View full abstract»

• ### A Harmonic-Selective Multi-Band Wireless Receiver With Digital Harmonic Rejection Calibration

Publication Year: 2019, Page(s):796 - 807
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A 30-mW multi-band receiver based on harmonic selection is presented. The prototype receiver employs a 32-phase non-overlapping local oscillator (LO) and is capable of simultaneously receiving multiple wireless signals arbitrarily located between 600 MHz and 3 GHz. The receiver achieves 2.4-5-dB noise figure (NF) and tolerates as large as -10-dBm out-of-band blockers. Employing a digital harmonic ... View full abstract»

• ### A Wake-Up Receiver With a Multi-Stage Self-Mixer and With Enhanced Sensitivity When Using an Interferer as Local Oscillator

Publication Year: 2019, Page(s):808 - 820
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An ultra-low power wake-up receiver with an energy-detection passive-RF architecture uses a multi-stage self-mixer that has a better conversion gain than the conventional envelope detector. The self-mixer, co-designed with the RF matching network, optimizes the sensitivity and minimizes the power consumption of the receiver. A wake-up receiver prototype in 0.13-μm CMOS operates at 550 MHz, consume... View full abstract»

• ### A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS

Publication Year: 2019, Page(s):821 - 833
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This paper presents a 31.5-GHz bandwidth (BW) 56-GS/s time-interleaved (TI) analog-to-digital converter (ADC) with 5.7-b effective number of bits (ENOB) and 5.2-b ENOB up to 17.5 and 27.1 GHz, respectively. To achieve the ENOB requirement over the entire Nyquist BW in 100-/200-Gb/s digital coherent receivers, several ENOB and BW enhancement techniques are presented. First, a low-noise parametric T... View full abstract»

• ### 34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers

Publication Year: 2019, Page(s):834 - 844
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High spectral efficiency offered by the coherent optical communication links makes them attractive for the nextgeneration optical communication links. Using advanced modulation schemes such as dual-polarization quadrature-amplitude modulation (DP-QAM) data rates beyond 200 Gb/s can be achieved. A key component of such links is the wide-bandwidth and high-linearity coherent optical receiver. In thi... View full abstract»

• ### A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS

Publication Year: 2019, Page(s):845 - 855
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This paper demonstrates a receiver (RX) for optical communications implemented in a 28-nm digital bulk-CMOS technology. Compact bandwidth (BW)-enhancement methods, such as inductor sharing and stacking, result in a measured BW of 27 GHz. By using these area-efficient techniques and a mixed-signal offset compensation system, a small active area of 0.009 mm2 is achieved. Noise and jitter ... View full abstract»

• ### An Energy-Efficient 3.7-nV/ $\surd$ Hz Bridge Readout IC With a Stable Bridge Offset Compensation Scheme

Publication Year: 2019, Page(s):856 - 864
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This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) that drives a continuous-time delta-sigma modulator (CTΔΣM). By exploiting the CCIA's ability to block dc common-mode voltages, the bridge's bias voltage may exceed the ROIC's supply voltage, allowing these voltages to be independently optimized. Since bridge... View full abstract»

## Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Jan Craninckx
Imec
Kapeldreef 75
B-3001 Leuven, Belgium
jssc.craninckx@gmail.com