# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Issue 7 • July 2018

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## Filter Results

Displaying Results 1 - 21 of 21

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2018, Page(s): C2
| PDF (114 KB)
• ### High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators

Publication Year: 2018, Page(s):1209 - 1222
| | PDF (4258 KB) | HTML

System accelerators (ACCs) improve performance and break power and utilization walls. They can be implemented by fixed-function hard macros or reconfigurable logic such as field-programmable gate arrays (FPGAs). For systems running various applications, dynamic reconfigurable ACCs offer a very attractive feature; however, the reconfiguration time is an unavoidable overhead. This paper proposes hig... View full abstract»

• ### Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring

Publication Year: 2018, Page(s):1223 - 1232
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Timing error predictors have a strong potential to reduce the worst case timing margins by monitoring timing slack of a design. However, these timing error predictors incur substantial amount of silicon area and power which limit the overall benefits in the system level. This paper presents a low overhead warning flip-flop (FF), which predicts setup time violations. It consists of a delay buffer a... View full abstract»

• ### An Adaptive Mechanism for Designing Efficient Snoop Filters

Publication Year: 2018, Page(s):1233 - 1240
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A common mechanism to ensure cache coherence is to issue snoop requests to all processors to check for the presence of cached data. Since most of snoop requests result in misses in caches and waste a lot of power, snoop filters are widely used to filter out unnecessary snoop requests to reduce power consumption. However, snoop filters also suffer from the similar problem that the false positive pr... View full abstract»

• ### Dynamic Reconfiguration of Thermoelectric Generators for Vehicle Radiators Energy Harvesting Under Location-Dependent Temperature Variations

Publication Year: 2018, Page(s):1241 - 1253
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Conventional internal combustion engine vehicles generally have less than a 30% of fuel efficiency, and the most wasted energy is dissipated in the form of heat energy. The excessive heat dissipation is a primary reason of poor fuel efficiency, but reclamation of the heat energy has not been a main focus of vehicle design. Thanks to thermoelectric generators (TEGs), wasted heat energy can b... View full abstract»

• ### Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Publication Year: 2018, Page(s):1254 - 1267
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Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/p... View full abstract»

• ### A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical RRAM

Publication Year: 2018, Page(s):1268 - 1276
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The 3-D vertical array architecture is considered to be a promising technology for emerging nonvolatile memories. But in 3-D vertical emerging nonvolatile memories, planar parasitic elements, vertical parasitic elements, and the sneak currents of the half-selected memory cells result in the delay of the read operation and read errors. This paper refers to the case of the 3-D vertical resistive swi... View full abstract»

• ### A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory

Publication Year: 2018, Page(s):1277 - 1289
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Delay units play an important role in bitline design for on-chip memory. Traditional delay units can be categorized into two types: passive ones and active ones. In this paper, a novel hybrid delay unit (combination of passive and active ones) using dummy through-silicon vias (TSVs) in 3-D on-chip memory is proposed for modern microprocessors. Dummy TSV delay units (DTDUs) are developed in multile... View full abstract»

• ### Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System

Publication Year: 2018, Page(s):1290 - 1300
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In this paper, we study the energy, performance, and reliability of 3-D horizontal 1-selector-1-resistor (1S1R) cross-point resistive random access memory (ReRAM) systems. We present access schemes which activate multiple subarrays with multiple layers in a subarray to achieve high energy efficiency through activating fewer subarray and good reliability through innovative data organization. We pro... View full abstract»

• ### Energy-Efficient Pedestrian Detection System: Exploiting Statistical Error Compensation for Lossy Memory Data Compression

Publication Year: 2018, Page(s):1301 - 1311
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Pedestrian detection represents an important application for embedded vision systems. Focusing on the most energy constrained implementations, systems have typically employed histogram of oriented gradients features and support vector machine classification, which leads to low detection accuracy (a log-average miss rate of 68% on the Caltech Pedestrian dataset). Additionally, single-scale d... View full abstract»

• ### Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method

Publication Year: 2018, Page(s):1312 - 1325
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Thermomechanical stress is one of the most important issues in performance and reliability analysis of through silicon via-based 3-D integrated circuits (3-D ICs), where an accurate numerical approach is generally needed to produce stress models and identify weak points in the structure. In this paper, we propose a knowledge-oriented nonuniform (KONU) refinement strategy for 3-D IC stress simulati... View full abstract»

• ### Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences

Publication Year: 2018, Page(s):1326 - 1339
| | PDF (4655 KB) | HTML

Stochastic computing (SC) often requires long stochastic sequences and, thus, a long latency to achieve accurate computation. The long latency leads to an inferior performance and low energy efficiency compared with most conventional binary designs. In this paper, a type of low-discrepancy sequences, the Sobol sequence, is considered for use in SC. Compared to the use of pseudorandom sequences gen... View full abstract»

• ### Data Reuse Buffer Synthesis Using the Polyhedral Model

Publication Year: 2018, Page(s):1340 - 1353
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Current high-level synthesis (HLS) tools for the automatic design of computing hardware perform excellently for the synthesis of computation kernels, but they often do not optimize memory bandwidth. As accessing memory is a bottleneck in many algorithms, the performance of the generated circuit could benefit substantially from memory access optimization. In this paper, we present a method and a to... View full abstract»

• ### Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Publication Year: 2018, Page(s):1354 - 1367
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As convolution contributes most operations in convolutional neural network (CNN), the convolution acceleration scheme significantly affects the efficiency and performance of a hardware CNN accelerator. Convolution involves multiply and accumulate operations with four levels of loops, which results in a large design space. Prior works either employ limited loop optimization techniques, e.g., loop u... View full abstract»

• ### Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks

Publication Year: 2018, Page(s):1368 - 1376
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Power analysis attacks (PAAs), a class of side-channel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a register-transfer level (RTL) countermeasure to increase the security of cryptographic devices against PAAs. We exploit the SDRR in a co... View full abstract»

• ### On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques

Publication Year: 2018, Page(s):1377 - 1390
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In this paper, we analyze the impact of the power supply noise and the power distribution network (PDN) impedance variation on the timing margin in both modes for ICs with multiple clock domains. We investigate the so-called intermodulation products (IMPs). We show that IMPs are mainly induced by the dependent nature of the transistors. We also provide experimental results showing that scan-based ... View full abstract»

• ### A Balunless Frequency Multiplier With Differential Output by Current Flow Manipulation

Publication Year: 2018, Page(s):1391 - 1402
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A balunless frequency doubler (FD) architecture which can provide differential output without any additional balun required is proposed in this paper. The architecture manipulates the desired second-harmonic currents around the doubler core by a multifunction network to avoid any leakage current path from the output current loop. Therefore, the output currents extracted from the same current loop ... View full abstract»

• ### A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm

Publication Year: 2018, Page(s):1403 - 1407
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This brief presents a low-power forward and reverse body bias (FRBB) generator with body bias (BB) switches to dynamically set BB voltage. The reverse BB (RBB) P-well generator uses pulse frequency modulation (PFM)-based switching capacitor power converter to achieve low power consumption in a wide load current range of 1–30 $mu ~text{A}$ View full abstract»

• ### A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator

Publication Year: 2018, Page(s):1408 - 1412
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State-of-the-art convolutional neural networks (CNNs) usually have a large number of layers and filter weights which bring huge computation and communication overheads. A general purpose instruction set architecture (ISA) is flexible but has low code density and high power consumption. The existing CNN-specific accelerators are much more efficient but usually are inflexible or require a complex co... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2018, Page(s): C3
| PDF (63 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu