[1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic

24-27 May 1993

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  • Proceedings of 1993 IEEE International Symposium on Multiple Valued Logic (ISMVL '93)

    Publication Year: 1993
    Request permission for commercial reuse | PDF file iconPDF (187 KB)
    Freely Available from IEEE
  • CMOS implementation and fabrication of the pseudo analog neuron

    Publication Year: 1993, Page(s):266 - 270
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    The pseudo-analog neuron (PAN) uses a transresistance amplifier and multivalued logic design techniques to implement the basic building blocks of artificial neural networks. The performance characteristics of PAN building blocks that were implemented in a standard 2-μm CMOS process are described. A two-layer network of PANs is used to implement various Boolean functions. The two-layer circuit c... View full abstract»

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  • Impact of interconnection-free biomolecular computing

    Publication Year: 1993, Page(s):271 - 276
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    A model of an interconnection-free computing system using biodevices is presented. The fundamental concept is the interconnection-free logic operation based on parallel distribution of logical information represented by varieties of molecules, and parallel selection using specificity of enzymes. The impact of interconnection-free computing on highly parallel processing architectures is analyzed th... View full abstract»

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  • Design of set-valued logic networks for wave-parallel computing

    Publication Year: 1993, Page(s):277 - 282
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    A design for set-valued logic (SVL) networks that provides a solution to interconnection problems in highly parallel VLSI systems is presented. The basic concept is frequency multiplexing of logic values, which enables the parallelism of electrical (or optical) waves to be used for parallel processing. This wave-parallel computing concept is capable of performing several independent binary functio... View full abstract»

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  • Gate model networks for minimization of multiple-valued logic functions

    Publication Year: 1993, Page(s):29 - 34
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    The use of gate model networks as a logic minimization method for multiple-valued logic functions is proposed. The gate model network is a kind of neural network constructed like and AND-OR two-level circuits using two gate models: an AND type gate model and an OR type gate model. The backpropagation (BP) method is used to train the network until it realizes the minimal solution. A solution is der... View full abstract»

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  • Design of multiple-valued linear digital circuits for highly parallel unary operations

    Publication Year: 1993, Page(s):283 - 288
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A design method for highly parallel multiple-valued linear digital circuits for unary operations using the concept of a cycle and a tree is proposed. In the circuit design, an analytical approach using a representation matrix is possible, so that the search procedure for optimal locally computable circuits becomes very simple. Some examples are shown to demonstrate the usefulness of the design alg... View full abstract»

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  • Single-chip realization of a fuzzy logic controller with neural network structure (NNFLC)

    Publication Year: 1993, Page(s):68 - 73
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    An NNFLC has been studied and designed employing the technology of current-mode multivalued CMOS and analog E2PROM. The NNFLC uses a neural network for knowledge memory instead of an if-then knowledge. This NNFLC behaves more intelligently than any traditional fuzzy logic control system. A single-chip application-specific integrated circuit (ASIC) realization of such NNFL has been desig... View full abstract»

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  • Some results on the decision and construction for Sheffer functions in partial k-valued logic

    Publication Year: 1993, Page(s):111 - 116
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    Decisions and construction for Sheffer functions in Pk and Pk* in partial k-valued logic are considered. The solution of these problems depends on the solution of the decision problem of completeness in P k and Pk* and is reduced to determining the minimal coverings of precomplete classes in P k<... View full abstract»

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  • A canonical disjunctive form of extended Kleene-Stone logic functions

    Publication Year: 1993, Page(s):36 - 41
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The authors define α-KS logic functions as infinite multiple-valued logic functions, adding a unary operation to fuzzy logic functions. The unary operation introduced is an extension of a unary operation of Kleene-Stone logic functions. Any α-KS logic function can be expanded into a disjunctive form, but the form is not determined uniquely. A special disjunctive form that can be determ... View full abstract»

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  • Synthesis and design automation of analog fuzzy logic VLSI circuits

    Publication Year: 1993, Page(s):74 - 79
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    A mathematical synthesis of current-mirror-based VLSI circuits suitable for design automation is proposed. In particular, a unified approach to synthesizing analog, current-mode CMOS fuzzy logic circuits is presented. The mathematical approach used for the fuzzy logic function synthesis is suitable for synthesis and design automation purposes. The approach is implemented in a prototype framework f... View full abstract»

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  • A fast algorithm for the disjunctive decomposition of m-valued functions. I. The decomposition algorithm

    Publication Year: 1993, Page(s):118 - 125
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    The binary function decomposition algorithm of V. Shen et al. (1971) is generalized to m-valued functions with m>2. The necessary condition for the decomposability for m-valued functions is obtained and used in generating candidate bound sets. A fast method for testing the necessary condition using partial partition tables whereby the decomposability of the function c... View full abstract»

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  • Multiple-valued logic design tools

    Publication Year: 1993, Page(s):2 - 11
    Cited by:  Papers (52)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    A brief overview of past progress in multiple-valued logic design is presented. The methods are considered with respect to the likely development of multiple-valued field programmable gate arrays. Look-up table based arrays are considered in some detail and an algorithm for mapping multiple-valued functions to such an array is presented. This algorithm uses reduced order multiple-valued decision d... View full abstract»

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  • Three-valued nonmonotonic logic

    Publication Year: 1993, Page(s):42 - 47
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The three-valued formulation of nonmonotonic logics is established. It is shown how to extend standard nonmonotonic logics to the three-valued case. It is also shown that a three-valued nonmonotonic logic called maximally ignorant (MI) logic can capture various major standard nonmonotonic logics as its special cases. It is argued that the three-valued nonmonotonic logic is closely related to modal... View full abstract»

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  • Multiple-valued logic functions represented by TSUM, TPRODUCT, NOT and variables

    Publication Year: 1993, Page(s):222 - 227
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    A class of multiple-valued logic functions (TO-functions, for short) expressed by TSUM, TPRODUCT, NOT, and variables is introduced, where TSUM is defined as min (x+y, p-1) and TPRODUCT is redefined as the product that is derived by applying De Morgan's laws to TSUM. It is shown that a set of TO-functions is not a lattice, and that in ternary logic TSUM can be expressed b... View full abstract»

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  • Functional completeness and weak completeness in set logic

    Publication Year: 1993, Page(s):251 - 256
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The functional completeness problems in r-valued set logic, which is the logic of functions mapping n-tuples of subsets into subset over r values, is discussed. It is shown that r-valued set logic is isomorphic to 2r-valued logic, meaning that the well-known completeness criteria in multiple-valued Post algebras apply to set-valued logic. Since Boolea... View full abstract»

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  • Systematic construction of natural deduction systems for many-valued logics

    Publication Year: 1993, Page(s):208 - 213
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A construction principle for natural deduction systems for arbitrary, finitely-many-valued first order logics is exhibited. These systems are systematically obtained from sequent calculi, which in turn can be automatically extracted from the truth tables of the logics under consideration. Soundness and cut-free completeness of these sequent calculi translate into soundness, completeness, and norma... View full abstract»

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  • Novel CMOS scan design for VLSI testability

    Publication Year: 1993, Page(s):82 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    A CMOS scan design that uses a ternary clock signal is presented. The routing of the long mode-control input signal is thus eliminated. Unlike previous efforts to eliminate the mode-control input, no additional MOS transistors are required in this design. Moreover, it has the same CMOS network as the traditional design; only the thresholds of the MOS transistors are varied. Computer simulations wi... View full abstract»

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  • A fast algorithm for the disjunctive decomposition of m-valued functions. II. Time complexity analysis

    Publication Year: 1993, Page(s):126 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    For part I see ibid., p.118-25. The time complexity of the fast algorithm for the disjunctive decomposition of m-valued functions, proposed in part I is studied. A probabilistic approach is used to estimate the time complexity for random m-valued functions, where several statistical properties of such functions are obtained and used in the analysis. It is shown that the time comp... View full abstract»

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  • Fast synthesis for ternary Reed-Muller expansion

    Publication Year: 1993, Page(s):14 - 16
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    A direct algorithm for calculating Reed-Muller coefficients under each fixed polarity is derived. This algorithm has not only a simple procedure but also much lower computational cost than the step-by-step flow graph algorithm with the polarities in Gray code order of D.H. Green (1989). Therefore, it lends itself to fast parallel computation View full abstract»

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  • Signed formulas and annotated logics

    Publication Year: 1993, Page(s):48 - 53
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    The relationship between signed formulas and annotated logics, two approaches that some authors have used to analyze multiple-valued logics (MVLs), is explored. A special case of the signed resolution rule is shown to be equivalent to, and thus to unify, the two inference rules, resolution and reduction, of annotated logic, raising the possibility of an SLD-style resolution rule for annotated logi... View full abstract»

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  • A repairable and diagnosable cellular array on multiple-valued logic

    Publication Year: 1993, Page(s):92 - 97
    Cited by:  Papers (1)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    A diagnosable and repairable k-valued cellular array is proposed, assuming a single fault, i.e., either a stuck-at-0 fault or a stuck-at-(k-1) fault of switches, occurs in the array. By building in a duplicate column iteratively, a fault-tolerant array can be constructed for the stuck-at-(k-1) fault, therefore, since the stuck-at-(k-1) fault need not be diagnose... View full abstract»

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  • Dreams for new-device-based superchips: from transistors to enzymes

    Publication Year: 1993, Page(s):140 - 149
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    The concept of multiplex computing is proposed to realize superchips free from interconnection problems. Parallel processing with multiplexable information carriers makes it possible to construct large-scale, highly parallel systems with reduced interconnections. Possible implementation approaches based on frequency-mode electronics, multiwave optoelectronics and bioelectronics are presented, and ... View full abstract»

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  • Multiple-valued logic computation circuits using micro- and nanoelectronic devices

    Publication Year: 1993, Page(s):164 - 169
    Cited by:  Papers (24)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The advantages of the negative transconductance of the resonant tunneling transistor (RTT) for implementing very efficient multivalued-logic (MVL) arithmetic building blocks are examined. Full adders are described for both the positive-digit 2.4 redundant number system and the signed-digit 4.3 minimum-redundant number system. The outlook for nanoelectronic MVL is considered View full abstract»

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  • Decimal addition and subtraction units using the p-valued decimal signed-digit number representation

    Publication Year: 1993, Page(s):228 - 233
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Parallel addition and subtraction of two numbers with signed-digit number representation can be performed in constant time. A signed-digit representation for radix r=10 (SD10R) is presented, and the usefulness of asymmetrical SD10R is considered. The authors propose p(qk. . .q1)-valued SD10Rs in which p is represented as a combination of qk to ... View full abstract»

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  • A representation of approximate reasoning with analogy

    Publication Year: 1993, Page(s):184 - 189
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    A scheme of approximate reasoning with analogical inference is proposed for purpose of flexible inference. This method uses truth value [0,1] based on possibility and assigns a truth value called certainty factor (cf) ∈[0,1] to the implication A→B. This inference conclusion is derived as a product of the truth value T(A) of the fact A and cert... View full abstract»

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