Proceedings of the European Conference on Design Automation.

25-28 Feb. 1991

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Displaying Results 1 - 25 of 101
  • EDAC. Proceedings of the European Conference on Design Automation

    Publication Year: 1991
    Request permission for commercial reuse | PDF file iconPDF (12 KB)
    Freely Available from IEEE
  • A performance analysis tool for performance-driven micro-cell generation

    Publication Year: 1991, Page(s):576 - 580
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A new method is presented to determine the power dissipation and propagation-delay time of small logical blocks (micro-cells). This method is a combination of the RC-tree and the macro modeling methods. It is a fast and accurate method, three orders of magnitude faster that SPICE, while the maximal error is ten percent. This method can be used in a performance-driven micro-cell generator for a sea... View full abstract»

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  • A hierarchical approach to timing verification in CMOS VLSI design

    Publication Year: 1991, Page(s):266 - 270
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    The author describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded ... View full abstract»

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  • Fast functional evaluation of candidate OBDD variable orderings

    Publication Year: 1991, Page(s):4 - 10
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    Symbolic simulation via ordered binary decision diagrams (OBDDs) is becoming more feasible each year. These representations are often very efficient under an appropriate ordering of the variables of the functions represented. Recently, heuristics for ordering variables have been developed, but due to the nature of heuristics, no single heuristic always produces an appropriate ordering. The authors... View full abstract»

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  • A proposed hardware fault simulation engine

    Publication Year: 1991, Page(s):570 - 574
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Fault simulation is a essential part of the design cycle and for large circuits it can be very time consuming. The authors examine the possibility of hardware acceleration of this process, especially that of sequential circuits. In order to achieve this, the architecture of a pipelined hardware simulation accelerator, the MANchester Simulation Engine (MANSE), is examined. Finally, the modification... View full abstract»

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  • Translating system specifications to VHDL

    Publication Year: 1991, Page(s):390 - 394
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations View full abstract»

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  • TAS: an accurate timing analyser for CMOS VLSI

    Publication Year: 1991, Page(s):261 - 265
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    A CMOS timing analyser using accurate delay models is presented. Switch-level analytic delays are derived from I/V characteristics of short-channel MOSFETS. A significant improvement in accuracy is obtained from the analysis of pertinent capacitances, modeling conflicts and slope effects in CMOS gates. The program handles large-scale circuits and gives the worst-case delays between circuit termina... View full abstract»

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  • Periodic signal suppression in a concurrent fault simulator

    Publication Year: 1991, Page(s):565 - 569
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Clock suppression has been proposed to take advantage of the periodic signals such as the clock present in synchronous designs. In clock suppression, no events due to the clock input are generated, but the information can be reconstructed as needed. In this paper, the authors present periodic signal suppression, which is a generalized form of clock suppression, as a means to suppress predictable e... View full abstract»

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  • The VLSI-programming language Tangram and its translation into handshake circuits

    Publication Year: 1991, Page(s):384 - 389
    Cited by:  Papers (87)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    Views VLSI design as a programming activity. VLSI designs are described in the algorithmic programming language Tangram. The paper gives an overview of Tangram, providing sufficient detail to invite the reader to try a small VLSI program himself. Tangram programs can be translated into handshake circuits, networks of elementary components that interact by handshake signaling. The authors have cons... View full abstract»

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  • Restructuring VLSI layout representations for efficiency

    Publication Year: 1991, Page(s):111 - 116
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    VLSI mask layouts usually have a hierarchical representation which serves to record the structure of the design while saving storage space. It is often convenient to work directly on such a representation for performing some operations. However for many other operations it is preferable to work on the flattened representation of the circuit. The authors look at the unnesting operation on layouts t... View full abstract»

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  • Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment

    Publication Year: 1991, Page(s):208 - 213
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The CAD implementation of a testability strategy for chips as designed with the Cathedral-II/2nd silicon compilation environment is presented. Emphasis is on the software tools accomplishing the test assembly. These tools are fully integrated with synthesis, place and route and module generation programs. The hierarchy present in the design has been exploited to assemble the test patterns in an hi... View full abstract»

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  • TATOO: an industrial timing analyzer with false path elimination and test pattern generation

    Publication Year: 1991, Page(s):256 - 260
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    TATOO is an industrial interactive timing analysis system evolved from recently developed false path elimination algorithms. These have been extended to perform more complex searches that facilitate the rapid survey of a network. An automatic test pattern generation mechanism which exercises the statically sensitizable paths has been developed. This forms a direct link to an electrical simulator. ... View full abstract»

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  • Symbolic implication in test generation

    Publication Year: 1991, Page(s):492 - 496
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    All test generation algorithms make use of symbolic algebra. The symbolic value that most test generators use is `X', to denote the unknown/do not care logic value. The other end of the spectrum is to shade each X differently to fully exploit the information contained in them. This is impractical due to combinatorial explosion that results from such coloring. In this paper, the authors explore use... View full abstract»

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  • Improved force-directed scheduling

    Publication Year: 1991, Page(s):430 - 435
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Presents a mathematical justification of the technique of force-directed scheduling and propose two modifications of the basic algorithm introduced by Paulin and Knight. The newly presented modifications improve the effectiveness of force-directed scheduling without affecting its time complexity. This is illustrated by an empirical performance analysis based on a number of problem instances View full abstract»

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  • Optimization of microcontrollers by partitioning

    Publication Year: 1991, Page(s):368 - 373
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Presents a new partitioning method for finite state machines (FSMs). The method is particularly well suited for μ-controller circuits. It consists in grouping the μ-instructions of the control graph into classes according to a compatibility property of the output values. Only one sequence of output values is then generated for all μ-instructions of a given class. The resulting structure i... View full abstract»

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  • Parallel switch-level simulation for VLSI

    Publication Year: 1991, Page(s):324 - 328
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Their target machines are medium-grain multiprocessors (shared memory or message passing machines) and they only consider model paralle... View full abstract»

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  • Formal sizing rules of CMOS circuits

    Publication Year: 1991, Page(s):96 - 100
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are g... View full abstract»

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  • A hardware design system based on object-oriented principles

    Publication Year: 1991, Page(s):459 - 463
    Cited by:  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Most hardware description languages and their environments are either based on imperative language concepts or on functional language concepts. The authors propose a hardware specification and simulation environment based on object-oriented principles. Object-oriented concepts such as classes, objects, inheritance and abstraction are considered in a design environment with the HiFi hardware design... View full abstract»

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  • Partitioning a network into n pieces with a time-efficient net cost function

    Publication Year: 1991, Page(s):177 - 182
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Discusses the generalization of the Fiduccia-Mattheyses linear time bi-partitioning algorithm to a linear-time n-partitioning algorithm. It uses a new heuristic cost function to evaluate the cost of arbitrarily large spanning trees in O(log n) time. Practical experiments show good results View full abstract»

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  • An approach to the analysis and test of crosstalk faults in digital VLSI circuits

    Publication Year: 1991, Page(s):72 - 79
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    The continuous reduction of the device size in integrated circuits and the increasing of the switching rate cause parasitic capacitances between conducting layers which might become dominant enough to provoke logic errors in the circuits. So, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this sort of faults. This paper presents a logic fault ... View full abstract»

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  • Hybrid compiled/interpreted simulation of MOS circuits

    Publication Year: 1991, Page(s):558 - 564
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The authors have developed a switch-level simulator that combines the speed of compiled simulation algorithms with the flexibility and fast set-up times of interpretive schemes. Compiled simulation is fast for simple sub-circuits and slow for certain complex ones. Interpretive schemes have a fast set-up time, but are slow in simulating simple circuits because of the overhead of the interpreted dat... View full abstract»

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  • Experiments with autonomous test of PLAs

    Publication Year: 1991, Page(s):503 - 509
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    An architecture for BIST of PLAs is presented, together with a testability analysis tool to assert test quality. The functionality of the PLA itself is utilized for stimuli generation. Experiments assert that the test patterns generated can be considered as random patterns with equal 1 and 0 probability of each input. Test quality is measured based upon computed fault detectability and estimated f... View full abstract»

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  • Decomposing data machines

    Publication Year: 1991, Page(s):378 - 382
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    Describes a new FSM decomposition algorithm which extracts a data register from a given FSM. The algorithm is a generalization of the standard minimization algorithm-it selects output values which, when stored in a separate data register, will make additional states in the control machine equivalent. Experimental results show that the algorithm is both effective and fast View full abstract»

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  • Electrical modelling of lossy on-chip multilevel interconnecting lines

    Publication Year: 1991, Page(s):106 - 110
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A self contained method for the electrical modelling of lossy 3-D multilevel interconnections has been developed. The method allows for the generation of a multiple coupled line model, compatible with SPICE-like CAD programs, from the interconnection line constants and parasitic coupling parameters which are computed by the so-called method of moments. The proposed method can be used for the analy... View full abstract»

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  • Fast heuristic algorithms for finite state machine minimization

    Publication Year: 1991, Page(s):192 - 196
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    A technique for the minimization of completely and incompletely specified sequential machines is described. By employing fast heuristic algorithms, it is shown that it is possible to effectively reduce large (121 states) finite state machines in reasonable computing time when compared to other methods. It has been shown that it is possible to achieve area/literal reductions in the range of 30-100%... View full abstract»

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