IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions

In this paper, the operation theory and the signal processes of the motor-engine rotate speed wireless measure apparatus are introduced. Because the most parts of its circuits are digital circuit, the process of its integration on a single chip is discussed in this paper. The hardware language VHDL is used in designing the circuit of the digital part, and the software Foundation of Xilinx Company ... View full abstract»

The phase noise and spurious spectrum are the key characters in direct digital frequency synthesizer (DDS) applied in radar and communications. The phase noise generated by phase truncation is analyzed in this paper. And phase noise generated by the size of ROM look-up table and the performance of DAC is also investigated. Meanwhile the methods designing about 60MHz, in 5Hz step, direct digital fr... View full abstract»

A hierarchical CDFG model designed as an intermediate representation for hardware/software (HW/SW) codesign is presented in this paper. A new concept of transport node, which represents the communication resources of the system, is proposed in this model. Hierarchical feature can be straightly obtained through extending the definition of nodes, allowing them to nest sub-CDFG recursively. Then it i... View full abstract»

A third-order sigma-delta (Σ - Δ) modulator implementation in a Digital Power Amplifier is presented in this paper. The operation is obtained by using a novel combination of architectural features, proper circuit structure selections, specific clocking strategies, and efficient circuit optimization algorithms. Measurement results from fabricated CMOS chip prototypes show a good match w... View full abstract»

In this paper we present a CAD tool based on a group of efficient algorithms to verify, design and optimize power/ground networks for standard cell model. Nonlinear programming techniques, branch and bound algorithms and Incomplete Cholesky decomposition conjugate gradient method (ICCG) are the three main parts of our work. Users can choose nonlinear programming method or branch and bound algorith... View full abstract»

With the increasing complexity of Microprocessor, the verification of the design becomes more and more important. This paper presented a simulation-based functional verification methodology to validate a 32-bit RISC microprocessor (named as FDU32). In the paper, pseudo-random generating and pipeline-focus generating are used as the main method to generate testbenches. Besides, the whole verificati... View full abstract»

The design and measurement results of a CMOS digital 2- and 4-FSK demodulator are presented in this paper. The demodulator is intended for use in direct-conversion high speed radio paging receivers. It is based on a zero-crossing counting and comparing scheme. To improve the bit error rate (BER) performance, a novel technique is utilized, which increases the decision accuracy by generating additio... View full abstract»

In this paper, an architecture and hardware implementation of the carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV is proposed. The proposed CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. To... View full abstract»

As the fast development of VLSI technology and the rapid increase of scale of chip, especially in the design of SOC, the original pattern of placing all pads on fixed positions cannot ensure high-quality power supply to each individual circuit blocks. In many cases, post-floorplanning power supply optimization cannot guarantee high-quality power supply under limited routing resources. Therefore, a... View full abstract»

The carrier lifetime and buffer-layer parameters determine the power dissipations of modern power devices. In this paper, based on simulation results, the trade-off relationships between the on-state conduction loss and turn-off loss of the 1800 V and 2400 V N-MCTs (N-MOS controlled thyristors) and IGBTs are studied comparatively. The simulation shows that the N-MCT has a better performance than t... View full abstract»

This paper analyses a general-purpose system for video acquisition and real-time video object detection, from the point of task flow, to acquire the flow structure of the system. Based on this, and the criteria of optimal system design, a system project based on the C6X DSP is put forward. This project reduces the hardware scale the furthest and improves resource utilization efficiency. View full abstract»

V² control technique of switching power converter is presented and analyzed in this paper. The small signal model and open-loop small signal transfer function of V² controlled switching power converters have been studied. As the example, the small signal performance analysis of V² controlled boost converter was performed. View full abstract»

A SOC design process with associated hierarchical hard IP reuse is proposed, in which hierarchical module partitioning can cope with the large scale of SOC. This methodology significantly reduces the time-to-market, complexity and potential for errors associated with SOC integration. View full abstract»

A universal baseband signal processing system for I/Q modem based on DSP and ASSP (application specific standard product) is proposed in this paper. By choosing an universal digital radio baseband processor (ASSP) as the co-processor of DSP, the computation burden on DSP has been released significantly. Compared with some traditional solutions to the issue, the technique discussed in this paper is... View full abstract»

With the high demand for reliability and performance, it is essential to determine an accurate estimation of maximum CMOS combinational circuit power consumption. However, for large-scaled circuits, the problem of determining the input patterns to induce maximum current and the maximum power is NP-complete. In this paper, a novel approach was proposed to obtain a lower bound of the maximum power c... View full abstract»

Microprogramming is used in VLIW processors and CISC processors. In the design of microprogrammed processors, to reduce the required microcode ROM area is performance-critical. In this paper, a novel method that can reduce the depth of microcode ROM is proposed. This method includes the design of addressing-entry and function-entry for each instruction. Meanwhile, with the aid of paged memory mana... View full abstract»

We present a new EEG inverse algorithm utilized for extracting multi-sources in EEGs. It is based on multiple signal classification (MUSIC). A delay-correlation matrix instead of the previous zero-delay-correlation matrix is introduced to conduct the signal-sub-space estimate in the MUSIC algorithm to get a better performance when coping with spatially coherent noise disturbances. The effectivenes... View full abstract»

With the development of VLSI circuits, the feature size has been decreased to the deep sub-micron level, and working frequency has reached 3 GHz. IC performance depends directly on parasitic interconnect inductance and resistance. In this paper, we propose a format to describe 3D hierarchical interconnects, and an approach automatically partitioning filaments in consideration of the skin effect. A... View full abstract»

Many research results show that TS (tabu search or taboo search) is depended on the selection of initial solutions. For good initial solutions, TS can find better results with quicker speed in the solution space, but poor initial solutions may decrease the TS convergence speed. This paper investigates and compares three common initializing algorithms (greedy, insertion and randomization) to solve ... View full abstract»

8VSB chip is used to decode the ATSC compliant cable channel signals. This paper presents a new approach to hierarchical layout design of 8VSB chip. Experiments show that our method can accelerate timing convergence and shorten design period. View full abstract»

In this paper, a design for a multi-channel high speed FIFO (First-in First-out) is presented. We know FIFO is widely used in various fields of data processing. Especially in the chip of high speed operation access, FIFO is a key device. This paper describes in detail data structure, algorithm and design method of the FIFO that is to support 128 logical channels and throughput maximum of 150 Mbps.... View full abstract»

A new supply approach of a DC-DC control circuit is proposed in this paper. Using this new approach, the control circuit energy is provided by the magnetic leakage energy. Operation states of the converter have been analyzed and parameters of components are given. View full abstract»