Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

The following topics are dealt with: semiconductor IP; formal verification; cooling; power management; defect oriented test; SAT and BDD techniques; low power design; mixed signal test; collaborative design; logic synthesis; symbolic techniques; EDA tools; analogue circuits; asynchronous circuits; BIST; DFT; co-design; SoC; embedded systems; reconfigurable architectures; analogue modelling; object... View full abstract»

Summary form only given, as follows. While process technologists are obsessed to follow Moore's curve down to nanoscale dimensions, design technologists are confronted with gigascale complexity. On the other hand, post-PC and post dotcom products require zero cost, zero energy yet software programmable novel system architectures to be sold in huge volumes and to be designed in exponentially decrea... View full abstract»

This paper presents a new formulation and an efficient solution of the power and ground mesh sizing problem. We use the key observations that (1) the drops in power and ground node potentials are due not only to currents drawn by the computing blocks, but also to those drawn by the clock buffers, and (2) changes of circuit component delays are linearly proportional to the power/ground IR-drops. Th... View full abstract»

Summary form only given. As VLSI technology advances, it forces changes in the business organization of the industry. Traditional vertically integrated semiconductor manufacturers are concentrating less on manufacturing as foundries such as TSMC, UMC, and Chartered grow. These foundries supply capacity not only to fables houses but also to even large semiconductor manufacturers. As a result, these... View full abstract»

In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced crosstalk noise for distributed RC coupling trees. The efficiency of our approach stems from the fact that only the five basic operations are used in the expressions: addition (x+y), subtraction (x-y), multiplication (x/spl times/y), division (x/y) and square root (/spl radic/x). The formulas do not req... View full abstract»

Summary form only given, as follows. Computer-aided design (CAD) has always been hardly understood by the CEO's of companies because it obeys rules (if any) very different from the process. A rich variety of CAD and TCAD solutions have been developed in Europe in the early days of the CAD industry. These solutions have come to introduce real innovations in the field, but because they were mostly i... View full abstract»

Summary form only given. The algorithms for static reordering of Reduced Ordered Binary Decision Diagrams (ROBDDs) rely on dependable properties for grouping of variables. Two such properties have been studied so far: keeping symmetric variables adjacent and minimizing the ROBDD width. However, counterexamples have been found for the both cases. In this paper, we introduce a new condition for grou... View full abstract»

Summary form only given. In Magma's BlastFusion/spl reg/ and BlastChip/spl reg/ software, very large blocks of logic (millions of gates) are handled flat. We implemented redundancy removal in a way that will allow it to run efficiently (fast, low memory usage) and robustly (no run time or memory explosion on any netlist) on industrial designs of up to several million gates. We achieve this without... View full abstract»

Summary form only given. A new method, algorithms and tool for the visualisation of a finite complete prefix (FCP) of a Petri net (PN) or a signal transition graph are presented. A transformation is defined that converts such a prefix into a two-level model. At the top level, it has a finite state machine (FSM), describing modes of operation and transitions between them. At the low level, there ar... View full abstract»

Summary form only given. This work presents the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied from the perspective of making easier and more practical the design of future GALS or GALA SoCs. This work focuses on high-level modeling and delay-insensitive implementations of low-power and reliable fixed and ... View full abstract»

Summary form only given. Cache memories are known to consume a large percentage of on-chip energy in current microprocessors. Direct-mapped caches are, in general, more energy efficient as they are simpler as compared to set-associative caches, and require no complex line replacement mechanisms. This study goes beyond performance-centric techniques, and proposes an energy-oriented optimization str... View full abstract»

Summary form only given. Reconfiguration is a very helpful feature that can improve the design life cycle of an embedded system and its quality. Reconfiguration means that software and hardware parts may be updated in the field. The update of system hardware implies the use of FPGAs in a shipped system. Normally, the update is done server controlled, which means that the active role comes from an ... View full abstract»

Summary form only given. In this paper we propose a novel approach for solving the Boolean satisfiability problem by combining software and reconfigurable hardware. The suggested technique avoids instance-specific hardware compilation and, as a result, achieves a higher performance than pure software approaches. Moreover, it permits problems that exceed the resources of the available reconfigurabl... View full abstract»

Summary form only given. An essential characteristic of embedded systems is real-time, but the commonly used specification techniques do not consider temporal aspects in general like fulfilment of high level timing requirements or dynamic reactions on timing violations. We show a new formal time model that fills this gap: timing requirements specify the timing behaviour of real-time systems. Diffe... View full abstract»

Summary form only given. The parametric fault diagnosis techniques play an important part in the field of analog fault diagnosis. These techniques, starting from a series of measurements carried out on a previously selected test point set, given the circuit topology and the nominal values of the components, are aimed at determining the effective values of the circuit parameters by solving a set of... View full abstract»

Summary form only given. Noise is an important consideration in the design of integrated circuits. Increased immunity to noise, however, typically comes at the expense of increased delay. So, it is very important to have an adequate noise immunity with a minimum penalty in performance. "Global" noise immunity schemes can be used when the noise is approximately the same on all nodes in the circuit;... View full abstract»

Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 /spl mu/m SiGe BiCMOS technology), presented here, illustrates how measurements results c... View full abstract»

Summary form only given. A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process. View full abstract»

Summary form only given. Weighted pseudorandom test generation (WPRTG) uses test sequences characterized by non-uniform distributions of test vectors in order to increase the detection probability of random resistant faults. Such non-uniform distributions are characterized by the values of signal probability of the CUT inputs (weights). Since different faults may require different distributions, a... View full abstract»

Summary form only given. Design methodologies for large designs produce circuits that consist of interconnections of functional blocks. If the blocks are large, as in core-based designs, they may be isolated for testing purposes (e.g., by test wrappers) such that different blocks can be tested independently. However, even if a test wrapper exists, it is advantageous to test functional paths that g... View full abstract»

Summary form only given. This paper considers the test-scheduling problem of a SoC. The proposed approach is based on a "sessionless" test scheme. It minimizes the system test time while respecting a power dissipation limit and test resource sharing constraints. Experimental results show that our approach outperforms other related test scheduling solutions. View full abstract»

Summary form only given. Reusability of tests is crucial for reducing total design time. This raises the problem of test knowledge transfer, physical test application and test scheduling. We present a formulation of the embedded core-based system-on-chip (SOC) test scheduling problem (ECTSP) as a network transportation problem. The problem is NP-hard and we present a O(mn(m+2n)) 2-approximation al... View full abstract»

Summary form only given. This work is a part of research directed towards checking methods development for approximate calculations executed by floating-point circuits in a mantissa unit. The problem of the truncated non-restoring division residue checking is solved. An efficient implementation of truncated division is provided, reducing almost twice the hardware amount and time of an iterative ar... View full abstract»