ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

23-25 Oct. 2001

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  • ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

    Publication Year: 2001
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    Freely Available from IEEE
  • Research on floorplanning

    Publication Year: 2001
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB)

    Summary form only given. We discuss our recent progress of block placement for floorplanning. We first extended zone refinement to cluster refinement. We then devised an O-tree floorplan representation for efficient and effective floorplan operations. Lately, we explored the relations between floorplan representations, i.e. slicing O-tree, sequence pairs, corner block list, O-tree, and twin binary... View full abstract»

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  • Technology roadmap on SOC testing: issues on SOC testing in DSM era

    Publication Year: 2001
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB) | HTML iconHTML

    Summary form only given. Deep sub-micron technology is rapidly leading to exceedingly complex, billion- transistor chips. By these technology evolutions, a system is integrated into a chip so called a system-on-a-chip (SOC). In order to bridge the productivity gap between available transistors and the ability to be designed in SOC, higher-level behavioral language and design re-use become more com... View full abstract»

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  • Authors index

    Publication Year: 2001, Page(s):889 - 893
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    Freely Available from IEEE
  • Challenges in RF analog integrated circuits

    Publication Year: 2001, Page(s):800 - 805
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (591 KB) | HTML iconHTML

    The recent aggressive downsizing of CMOS devices makes it potential to implement RF front-end in the CMOS process, but RF circuits have some special demands which the standard digital CMOS process does not consider: low noise, high linearity, high quality passive components. These demands present the main barriers to implement the RF front-end in CMOS process and need special efforts to get good p... View full abstract»

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  • Design and VLSI implementation of an asynchronous low power microcontroller

    Publication Year: 2001, Page(s):797 - 799
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (246 KB) | HTML iconHTML

    A novel VLSI design and implementation of a low power 8-bit microcontroller using asynchronous logic is proposed in this paper. Taking advantage of the low power potential of asynchronous logic, the 2-stage pipelined MCU is carefully designed by chosen proper architecture as well as suitable asynchronous signal protocols which including a combination of a specific "Completion Detection Method" and... View full abstract»

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  • MT ARM: multithreading implementation in Arm7 architecture

    Publication Year: 2001, Page(s):793 - 796
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    The ARM7 processor can only reduce preserving and recovering overhead on context-switch, but it can do nothing about pipeline hazard. This paper presents one kind of multithreading implementation of ARM7 Architecture (called MT ARM) to achieve high-speed responsibility to handle events by eliminating the pipeline hazards. The pipeline of MT ARM is composed of four stages: Thread Select, Instructio... View full abstract»

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  • Coupling computation of the BEM and FDM in 3D capacitance extraction

    Publication Year: 2001, Page(s):716 - 719
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB) | HTML iconHTML

    When using the boundary element method (BEM) to calculate the capacitance of three-dimensional VLSI interconnects with multiple dielectrics, a significant error can occur if some dielectrics do not contain a conductor. We present a new algorithm of coupling computation of BEM and the finite difference method (FDM) to resolve the problem. This algorithm still uses BEM for dielectrics which contain ... View full abstract»

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  • A modified microprogramming control for FPU

    Publication Year: 2001, Page(s):789 - 792
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB) | HTML iconHTML

    A novel architecture and control of the FPU LSC87 chip, which is instruction compatible with INTEL 8087 coprocessors, is described. The modified microprogramming control presented here is best suited for complicated processes, including the supporting of 7 floating point numbers and binary or decimal integers, the implementation of IEEE standard 754 floating point arithmetic, as well as the comput... View full abstract»

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  • Hierarchical h-adaptive computation in VLSI interconnect capacitance extraction

    Publication Year: 2001, Page(s):712 - 715
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    A hierarchical h-adaptive method based on BEM is proposed for VLSI parasitic capacitance extraction. In h-adaptive methods, high computational accuracy is guaranteed by auto refinement of the boundary elements. A new auto refinement method is introduced by property storage of the boundary elements. It is more effective than the old methods in the stability of adaptive computation. A new error esti... View full abstract»

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  • Optimizing the design for microdisplay on silicon, creating IP modules for a new type of SOC

    Publication Year: 2001, Page(s):785 - 788
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (401 KB) | HTML iconHTML

    A microdisplay chip on silicon is a piece of multi-function and multi-structure SOC (system on chip). From the common circuit of the microdisplay chip, we are able to form several independent IP modules. Then we design a suite of 0.8 μm CMOS basic libraries and IP modules for a microdisplay on silicon with CADENSE. Additionally, we demonstrate the flexible design of a capacitor for the microdis... View full abstract»

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  • Parameter extraction of BSIM based on S3 theory

    Publication Year: 2001, Page(s):708 - 711
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB) | HTML iconHTML

    We develop a novel algorithm for parameter extraction of semiconductor devices. The S3 algorithm, which is functional for NP-hard problems in discrete space, is applied to the parameter extraction of BSIM (Berkeley Short-channel IGFET Model). By using this algorithm, a relatively large number of model parameters can be optimized globally and extracted simultaneously. As to BSIM1, two di... View full abstract»

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  • CEP: a clock-driven ECO placement algorithm for standard-cell layout

    Publication Year: 2001, Page(s):118 - 121
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (542 KB) | HTML iconHTML

    Incremental placement or ECO (engineer change order) placement is a new field in VLSI layout to meet the demand of high performance design. In this paper, a novel clock-driven ECO placement algorithm, CEP, is presented for standard cell layout design. It considers clock skew information in the placement stage, modifies the positions of cells locally to make better preparation for the clock routing... View full abstract»

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  • A platform for system-on-a-chip design prototyping

    Publication Year: 2001, Page(s):781 - 784
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    System prototyping is an important step in embedded system design, it can be used to validate the system functionality, performance and real time response to environment. A platform containing a microcomputer and a prototyping board is built for system-on-a-chip prototyping. A simple system-on-a-chip prototype reacting with its environment is built demonstrating the usage of the platform. The on c... View full abstract»

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  • Mixed-signal behavioral modeling for QPSK digital communication system

    Publication Year: 2001, Page(s):704 - 707
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB) | HTML iconHTML

    In this paper, a behavioral model of the QPSK digital communication system is presented using VHDL-AMS. The whole system can be divided into several parts. So, on the basis that the behavioral models of the parts are established first, the behavioral model of the system can be accomplished with the top structural description. Then the models can be verified by simulation View full abstract»

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  • A flash IC card with programmable security code

    Publication Year: 2001, Page(s):584 - 587
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (314 KB) | HTML iconHTML

    A flash IC card with programmable security code and embedded 2 Kb flash memory has been developed. Using the NORST (NOR with Select Transistor) flash EEPROM cell make this flash memory suitable for the embedded applications. The needed high positive and negative boosted voltages when programming and erasing are provided by the Dickson charge pump on chip. Two circuit techniques are proposed for th... View full abstract»

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  • An efficient congestion optimization algorithm for global routing based on search space traversing technology

    Publication Year: 2001, Page(s):114 - 117
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (414 KB) | HTML iconHTML

    In this paper, we present an efficient congestion optimization algorithm for global routing based on search space traversing technology. In this method, we adopt stochastic optimization, deterministic optimization and a local enumeration strategy to dynamically reconstruct the problem structure and make the "transition" from a local minimum point. Thus, we can reach other parts of the search space... View full abstract»

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  • A debug sub-system for embedded-system co-verification

    Publication Year: 2001, Page(s):777 - 780
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB) | HTML iconHTML

    With the development of VLSI, embedded system is growing sharply. A new methodology, Co-design, appeared to meet needs of embedded system designing. System designers require good EDA tools, which support Co-design methodology. Debug is an important part of design process, so we improved a debug subsystem to fit Co-design. Different from traditional software debug tools, the new debug system was de... View full abstract»

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  • The design of a novel low-power and high-precision voltage testing circuit

    Publication Year: 2001, Page(s):637 - 640
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (299 KB) | HTML iconHTML

    This paper presents the design of a novel low-power and high-precision voltage testing circuit. The circuit consists of a temperature-insensitive reference voltage generator and a voltage follower to eliminate the loading effect. The circuit has been fabricated in 0.8 μm CMOS technology and its performance has been measured, which shows that the circuit functions are consistence with the theore... View full abstract»

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  • An SC CCIR-601 video restitution filter with 13.5 Msample/s input and 108 Msample/s output

    Publication Year: 2001, Page(s):374 - 377
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (589 KB) | HTML iconHTML

    This paper presents a design and implementation of a low-power switched-capacitor filter for NTSC/PAL digital video restitution system with CCIR-601 standards. The filter which employs optimized structures including coefficient-sharing, spread-reduction, semi-offset-compensation, mismatch-shaping, double-sampling and analog multirate and multistage techniques achieves linear-phase lowpass response... View full abstract»

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  • Parameterized IP core design

    Publication Year: 2001, Page(s):744 - 747
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (421 KB) | HTML iconHTML

    In the era of Systems-on-Chip (SoC), in order to reduce product cycle time and development cost, people have developed an IP-based SoC design methodology. However, this new methodology raises more issues for IP core creation. In order to make an IP core more flexible for SoC, the core should be configurable. Such configurability requires a new focus on "parameterized IP core". In this paper, we de... View full abstract»

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  • Real-time duplex digital video surveillance system and its implementation with FPGA

    Publication Year: 2001, Page(s):471 - 473
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (305 KB) | HTML iconHTML

    Real-time digital video surveillance systems are used in many fields, such as banks, buildings and supermarkets. The core part of system is a video multiplexer. In this paper, a novel hardware design of real-time duplex digital sixteen-picture processor is implemented with only one FPGA chip. Functions of the real-time digital video multiplexer include picture dividing/joining, video motion detect... View full abstract»

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  • Library building technique for high-reliability submicron ASIC

    Publication Year: 2001, Page(s):163 - 166
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    This paper describes the technique of submicron ASIC design on reliability and the methodology of ASIC library building. Additionally, this paper has represented the results of the research View full abstract»

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  • Parallel behavior-level simulator based on VHDL-AMS [mixed circuit simulation]

    Publication Year: 2001, Page(s):700 - 703
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (325 KB) | HTML iconHTML

    This paper proposes a novel approach that makes use of a software package named parallel virtual machine (PVM), which allows a researcher to use workstations as nodes in a parallel processing environment to perform a large-scale simulation. The parallel scheme is described, and the computational power and cost effectiveness of PVM are demonstrated on the problem of simulating mixed circuits View full abstract»

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  • A high speed 0.25 μm 64-bit CMOS adder design

    Publication Year: 2001, Page(s):581 - 583
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB) | HTML iconHTML

    A fast 64-bit dynamic adder has been designed for high performance microprocessors in 2.5-V 0.25-μm 1-poly 5-metal CMOS technology. Fast carry signals can only be obtained by fast G (Generation) and P (Propagation) terms. Integrating dynamic CMOS logic, the Kogge & Stone algorithm and a new circuit architecture, the adder comprises 7 k FETs and has 660 ps addition latency under nominal cond... View full abstract»

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