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Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001

23-26 Sept. 2001

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Displaying Results 1 - 25 of 90
  • Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001

    Publication Year: 2001
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    Freely Available from IEEE
  • The in-car computing network: an embedded systems challenge

    Publication Year: 2001, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB)

    Summary form only given, as follows. Modern vehicles are in fact computer networks on wheels. Up to 60 electronic control units are connected using various networking technologies such as CAN (Controler Area Network) or MOST (optical fibres for multimedia content). Many of the control units use state of the art microcontrollers and have complex analog and digital interfacing circuitry. Software is... View full abstract»

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  • Moore's law meets Shannon's law: the evolution of the communication's industry

    Publication Year: 2001, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (74 KB)

    Summary form only given, as follows. The insatiable demand for data and connectivity at the user level, driven primarily by the everincreasing horsepower of the desktop computer, has dramatically impacted the evolution of the communications market. In a period of 20 years we have progressed from 300 baud modems to multi-terabit fiber backbones. However, the downside to rapid evolution is that it o... View full abstract»

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  • Gate sizing to eliminate crosstalk induced timing violation

    Publication Year: 2001, Page(s):186 - 191
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (663 KB) | HTML iconHTML

    Digital circuits manufactured in deep sub-micron technologies may experience crosstalk-induced delay and noise signals. Crosstalk-induced delay can be quite significant and sensitive to the driver strength of coupling neighbors. In this paper, we propose gate-sizing techniques to reduce delay in presence of crosstalk effects. The techniques are based on our (2001) previously proposed crosstalk awa... View full abstract»

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  • Author index

    Publication Year: 2001, Page(s):557 - 559
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    Freely Available from IEEE
  • Efficient function approximation for embedded and ASIC applications

    Publication Year: 2001, Page(s):507 - 510
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    In embedded systems and application specific integrated circuits (ASICs) that typically do not have a floating-point processor, measured data or function-sampled data is commonly described by means of an analytic function derived using standard numerical methods. The resultant errors are not caused by rounding the coefficients but by translating a real solution to a restricted fixed-point environm... View full abstract»

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  • A single-multiplier quadratic interpolator for LNS arithmetic

    Publication Year: 2001, Page(s):178 - 183
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB) | HTML iconHTML

    Linear interpolation requires a single multiplication but is significantly less accurate than quadratic interpolation. The latter requires two multiplications. Two novel quadratic interpolation schemes are shown that approximate the functions required by the logarithmic number system (LNS) with more accuracy than linear interpolation using only a single multiplication. One method uses two ROMs to ... View full abstract»

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  • RC-in RC-out model order reduction accurate up to second order moments

    Publication Year: 2001, Page(s):505 - 506
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB) | HTML iconHTML

    In this paper, we present a RC-in RC-out model order reduction method which takes RC circuits and accurate reduced models which can be realized using passive RC elements. The reduced models are accurate up to 2nd order moment and hence are more accurate than the first order moment matching based algorithm. The runtime and reduction ratios of our method are not dependent on the number of ports, whi... View full abstract»

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  • Alloyed path-pattern scheme for branch prediction

    Publication Year: 2001, Page(s):534 - 537
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    For more accurate branch prediction, global as well as local histories have been studied and a need for hybrid history has emerged. Not only do different parts of a program require different types of histories, but some branches dynamically vary the type of history. To solve this problem, schemes involving dynamic selectors as opposed to static have been proposed. Initially, history represented th... View full abstract»

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  • Selecting a well distributed hard case test suite for IEEE standard floating point division

    Publication Year: 2001, Page(s):89 - 96
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB) | HTML iconHTML

    We investigate two sets of hard to round p×p bit fractions arising from division of a normalized p bit floating point dividend by a normalized p bit floating point divisor. These sets can be characterized by the p×p bit fraction's quotient bit string, beginning with or just after the round bit, having the maximum number (p-1) of repeating like bits, specifically 00...01 or 11:..10 for ... View full abstract»

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  • Crosstalk noise estimation for generic RC trees

    Publication Year: 2001, Page(s):110 - 116
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    We propose an estimation method of crosstalk noise for generic RC trees. The proposed method derives an analytic waveform of crosstalk noise in a 2-π equivalent circuit. The peak voltage is calculated from the closed-form expression, and the crosstalk induced delay is estimated using the derived noise waveform. We also develop a transformation method from generic RC trees with branches into the... View full abstract»

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  • Clear and present tensions in microprocessor design

    Publication Year: 2001, Page(s): 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (41 KB)

    First Page of the Article
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  • Design alternatives for parallel saturating multioperand adders

    Publication Year: 2001, Page(s):172 - 177
    Cited by:  Papers (5)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    Parallel saturating multioperand adders significantly improve the performance of global system for mobile (GSM) speech coders by giving compilers and assembly language programmers the ability to parallelize loops containing saturating dot products, while maintaining GSM compliant results. This paper presents four designs for parallel saturating multioperand adders. These designs have at most one c... View full abstract»

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  • A hierarchical dependence check and folded rename mapping based scalable dispatch stage

    Publication Year: 2001, Page(s):249 - 254
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    In a superscalar pipeline, the dispatch stage performs register renaming, which involves map table lookup logic and dependence check logic. Both subtasks do not scale well with the dispatch width of the processor. The number of comparators necessary for the dependence check logic grows quadratically with the dispatch width of the processor. The rename map table's word line capacitance scales linea... View full abstract»

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  • High performance parallel fault simulation

    Publication Year: 2001, Page(s):308 - 313
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB) | HTML iconHTML

    Parallel simulation on multiple processors is one method by which fault simulation time in large circuits can be reduced significantly. To realize near-linear execution time gains from parallel processing, the parallelization techniques used should result in an even computational load distribution across the processors in the parallel system. Fault simulation can be parallelized either by partitio... View full abstract»

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  • An algorithm for dynamically reconfigurable FPGA placement

    Publication Year: 2001, Page(s):501 - 504
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    In this paper, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the conside... View full abstract»

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  • Reducing cache pollution of prefetching in a small data cache

    Publication Year: 2001, Page(s):530 - 533
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    The need for a low power, high performance embedded processor has grown at a very fast pace in recent years. Embedded processors require smaller cache size for low power system-on-a-chip consideration. Decreasing cache size leads to reduced power consumption because a smaller cache has less capacitance from the bit array size as well as smaller drivers in decoder or peripheral circuitry.. Unfortun... View full abstract»

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  • A functional validation technique: biased-random simulation guided by observability-based coverage

    Publication Year: 2001, Page(s):82 - 88
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB) | HTML iconHTML

    We present a simulation-based semi-formal verification method for sequential circuits described at the register-transfer level. The method consists of an iterative loop where coverage analysis guides input pattern generation. An observability-based coverage metric is used to identify portions of the circuit not exercised by simulation. A heuristic algorithm then selects probability distributions f... View full abstract»

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  • BDD variable ordering by scatter search

    Publication Year: 2001, Page(s):368 - 373
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    Reduced ordered binary decision diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions which are frequently used in VLSI design automation. The variable ordering largely influences the size of the BDD, varying from linear to exponential. In this paper we study BDD minimization problem based on scatter search optimization. The results we obtained are very enco... View full abstract»

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  • A heuristic for multiple weight set generation

    Publication Year: 2001, Page(s):513 - 514
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    The number of weighted random patterns depends on the number of deterministic test patterns with a low sampling probability. The weight set that is extracted from the deterministic pattern set with high sampling probability reduces the number of test patterns. In this paper we present a new deterministic pattern selection algorithm which generates high performance weight sets by removing determini... View full abstract»

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  • Performance optimization by wire and buffer sizing under the transmission line model

    Publication Year: 2001, Page(s):192 - 198
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    As the operating frequency increases to giga hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the transmission line behavior for delay computation. We present an analytical formula for the delay computation under the transmission line model. Extensive simulations with SPICE show the high fidelity of the formula. Compa... View full abstract»

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  • Performance impact of addressing modes on encryption algorithms

    Publication Year: 2001, Page(s):542 - 545
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB) | HTML iconHTML

    Encryption algorithms commonly use table lookups to perform substitution, which is a confusion primitive. The use of table lookups in this way is especially common in the more recent encryption algorithms, such as the AES finalists like Twofish and MARS, and the AES winner, Rijndael. Workload characterization studies indicate that these algorithms spend a significant fraction of their execution cy... View full abstract»

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  • Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits

    Publication Year: 2001, Page(s):104 - 109
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2 GHz has caused crosstalk noise to become a serious problem, that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In particular, we provide closed-form expr... View full abstract»

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  • A timing-driven macro-cell placement algorithm

    Publication Year: 2001, Page(s):322 - 327
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    The timing-driven macro-cell placement algorithm described is based on the force-directed technique. The proposed star net model enables more accurate timing analysis, hence path delay constraints can be handled. In addition, the placer provides functions such as determination of cell orientation, routing estimation and pad placement. The algorithm is iterative and incremental, allowing flexibilit... View full abstract»

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  • Jitter-induced power/ground noise in CMOS PLLs: a design perspective

    Publication Year: 2001, Page(s):209 - 213
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB) | HTML iconHTML

    CMOS phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the stati... View full abstract»

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