Symposium 1993 on VLSI Circuits

The adoption of video coding standards, the deployment of digital communication services and the availability of high performance full custom VLSI will open up a wide range of exciting new multimedia products and services. These devices stretch the limits of our silicon technology but will continue to benefit from advances in processing, circuit design, packaging and CAD tools. View full abstract»

In this paper we applied the method known as checking experiments to generate test sequences for sequential circuits under the stuck-at fault model. To design a sequential circuit having a distinguishing sequence is a key in this method. As modification techniques of sequential circuits, two testable design techniques have been considered. One is a testable design technique at the state transition... View full abstract»

Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to ... View full abstract»

Describes a CISC superscalar microprocessor. It executes 126 instructions with 14 addressing modes, which include floating-point processing fully compatible with the ANSI/IEEE 754-1985 standard. A 64-entry branch-always target buffer (BTB) enables O-cycle branching. An 8-entry return buffer (RB) reduces execution cycles of returns from a subroutine. The processor incorporates 8-kB instruction and ... View full abstract»

Recently, the demand for using low-end RISC-CPUs in small equipment devices such as handy terminals is increasing. On-chip cache and direct connections to page mode DRAM is one of the best solution to achieve high-performance and low-cost systems. However, integrating the conventional cache will have a penalty of cache miss increase when page mode DRAM is used for burst transfer mode. This paper d... View full abstract»

The synchronous Tag RAM reported in this paper holds addresses and status bits of cached data and can be used to build a secondary cache system of up to 16MBytes with external commodity synchronous SRAMs. In order to handle the large secondary cache, the present Tag RAM contains 1.189Mbit of 4T SRAM cells, the largest capacity ever reported for a Tag RAM. Short cycle time and small clock to D/sub ... View full abstract»

It has long been customary for silicon-based IC designers to restrict their attention to resistive and capacitive effects when considering circuits confined to the chip. The simple justification for this approach has been that typical "RC" time constants in this environment dwarf the "time of flight" of light across the distances involved. However, with the advent of large chips running at upwards... View full abstract»

We have presented a novel technique that allows skew-free distribution of digital signals with known and controllable arrival times. The technique requires adjustments and measurements only at the sender. Our method is based on measuring the round trip delay of a signal and then adjusting it with a pair of matched delay lines. This technique can be modified to work without extra wiring, and is eff... View full abstract»

We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use cells contain... View full abstract»

A method of measuring digital noise in an analog circuit such as an A/D converter by a voltage comparator is proposed and the noise dependence was measured by a fabricated test chip. For mixed-signal ICs, it was shown that the effect of digital noise can be considerably reduced by using a differential configuration in analog circuits. The effect of digital noise can be further reduced by lowering ... View full abstract»

A complementary emitter follower composed of a direct-coupled npn transistor and a capacitor-coupled pnp transistor is proposed. Low power dissipation and good noise removing capability can be obtained by this coupling scheme. An ECL gate with this complementary emitter follower is 63% faster and has 4 times better load driving capability than a conventional ECL gate. View full abstract»

The self-biased, feedback-controlled, active-pull-down emitter follower is a very efficient and superior circuit applicable to high-speed low-power bipolar/BiCMOS digital VLSIs. The circuit is effective because the biasing, inverting, level-shifting, and coupling functions are simply merged into a small number of devices and is versatile for logic implementations because it does not need any extra... View full abstract»

This paper introduces a new, self-adjusting active pull-down circuit for ECL that uses voltage regulation rather than traditional load-dependent capacitive coupling. Depending on the application, a 3.5X speed improvement over traditional ECL at comparable power, or a 7.1X power reduction at comparable performance can be obtained. A voltage regulation and distribution circuit for the required V/sub... View full abstract»

This paper describes design techniques for multi-GHz digital bipolar circuits that operate with supply voltages as low as 1.5 V. Examples include a multiplexer (MUX), a latch, two exclusive OR (XOR) gates, and a buffer/level shifter, circuits that typically employ stacked differential pairs in conventional ECL and hence do not easily lend themselves to low voltage operation. When implemented in a ... View full abstract»

This mixed analog-digital fuzzy logic inference processor chip calculates the result of an inference over a 32-rule knowledge base in parallel. Simulations predict a computation time for the array of about 2 /spl mu/sec. The processor interface behaves like a static RAM, but internal computation is performed in the analog domain to an expected precision of 6 bits. The completed chip measures 7 mm ... View full abstract»

We discuss a digital neuroprocessor using quantizer neurons designed for character or image recognition and learning. The number of synapses in a neural network is a very important factor for the accurate recognition of images. A neural network with a large amount of synapses can achieve high recognition accuracy, however, it makes the processing speed lower because of the large number of network ... View full abstract»

A JPEG compliant Huffman decoder circuit has been developed. The circuit executes at 27 MHz in order to maintain image data transfer at CCIR 601 video rates. The circuit detects and decodes variable length Huffman codes in a single clock cycle by searching among all Huffman codes in the current table. The circuit utilizes a CAM with mask bits to perform this rapid search. The architecture also uti... View full abstract»

The design of an asynchronous sample-rate converter for digital audio applications is presented. Input and output sample rates are sensed automatically. The converter can be slaved to both input and output sample clocks that need not be synchronous to the chip's master clock. Sample rate ratio changes of up to 2:1 in either direction can be accommodated. Measured output SNR while driven by a 10 kH... View full abstract»

A low-power charge recycle refresh featuring alternative operation of two arrays was proposed. After amplification in the first array, the charges in that array are transferred to the other array, where they are recycled for half the amplification there. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is als... View full abstract»

To reduce self refresh mode current, a temperature detecting circuit, back bias generator and voltage down convertor, are developed. Using these circuits in a 16M DRAM, 33 /spl mu/A consuming current in self refresh mode has been realized at Vcc=5V, Ta=25 /spl deg/C. View full abstract»

Subthreshold-current reduction, especially at room-temperature operation, is one of the key design issues in the gigabit era. Despite its importance, however, a scheme for it has not been proposed. In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed. They can drastically reduce even the active curr... View full abstract»

The reduction of exponentially increasing standby subthreshold current due to threshold-voltage (V/sub T/) scaling is one of the most important design issues for giga-scale LSIs operating at room temperature. This paper proposes a switched-source-impedance CMOS circuit featuring the subthreshold current reduction of LSIs in standby mode by 34 decades with minimum speed penalty in active mode. The ... View full abstract»

Portable equipment such as compact disc players, camcorders, and cellular phones employ both analog and digital LSIs. In the future, portable equipment will use more complicated processing, such as audio/video compression and decompression technologies which need many more logic gates. But the use of analog circuits will continue in future portable equipment, even if such complicated digital proce... View full abstract»

There will always be chips designed with the highly manual approaches required to extract the utmost in performance. However, unless the market for a chip is well into the hundreds of millions of dollars, this approach may not be economically justified. A better approach for the vast majority of chip designs is to start with a methodology with proven high productivity, and carefully examine extens... View full abstract»