[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

21-25 Sept. 1992

Filter Results

Displaying Results 1 - 25 of 123
  • A tutorial on GaAs vs silicon

    Publication Year: 1992, Page(s):281 - 287
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (487 KB)

    The physical properties of GaAs and silicon are described, and the advantages and disadvantages of GaAs over silicon in terms of physics are reported. The implications of physical properties and circuit techniques for computing and communication applications are addressed in terms of ASICs.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Tutorial on design for testability

    Publication Year: 1992, Page(s):139 - 142
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (270 KB)

    Testability must be incorporated in all phases of an ASIC design, including wafer level, chip level, I/O level, and board/system level. Level-sensitive scan design (LSSD) is a design technique that uses latches and flip-flops that are level sensitive as opposed to edge triggered. The basic approach of LSSD is to make a sequential network appear like combinatorial logic during testing by logically ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Timing driven placement of pads and latches

    Publication Year: 1992, Page(s):30 - 33
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB)

    A heuristic approach to the placement of I/O pads and sequential elements prior to the layout of a VLSI circuit is presented. The input information for the algorithm is the structure of the circuit and its path delay constraints. Experimental results suggest that the loss in performance can be substantial (on the order of 10%) when pads and/or latches are placed without consideration of performanc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit (Cat. No.92TH0475-4)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (15 KB)
    Freely Available from IEEE
  • BAT: an ASIC I/O interface analysis and synthesis tool

    Publication Year: 1992, Page(s):483 - 486
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A buffer analysis tool (BAT) that produces an electrical model of the chip interface, given an I/O buffer placement and the package type of the device, is described. BAT can estimate the peak switching ground noise voltage for a given configuration. Alternatively, if the I/O pin order is flexible, the tool can also synthesize an optimum pin order that will result in minimum switching noise voltage... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pre-design consideration and evaluation for ASICs

    Publication Year: 1992, Page(s):249 - 252
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A new design methodology is used to evaluate the difference in performance when implementing the same design using two different ASIC libraries. Multiple dimensions of the design space are considered yielding a better evaluation of the design in hand. An arithmetic logic unit (ALU) is designed using both a standard cell library and a data path library. A cost function is evaluated for both cases a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VLSI focal-plane array processor for morphological image processing

    Publication Year: 1992, Page(s):423 - 426
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    A full-custom mixed-signal VLSI design for high-speed morphological image processing is developed by combining a two-dimensional fine-grain parallel array architecture with on-chip focal-plane photodetectors and transmitters. An 8×8 array processor prototype chip is designed in a 1.2-mm×1.2-mm silicon area using the MOSIS 2-μm CMOS process View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • VLSI CMOS implementation of the shuffleout ATM switch interconnection matrix

    Publication Year: 1992, Page(s):87 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The VLSI design and implementation of the shuffleout broadband switch interconnection matrix are described in order to show its feasibility with current CMOS technology. It satisfies simultaneously the requirements for ATM switching and for ASIC industrial manufacturing. The shuffleout routing principles are briefly summarized and the design approach is discussed. The switching element major block... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A simulation based strategy for mixed-signal testing

    Publication Year: 1992, Page(s):363 - 367
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    A testing strategy that links design with test for mixed-signal devices in order to solve the testing problems at their roots is described. Test generation is achieved through mixed-mode simulation of both analog and digital circuitry on a single chip. The key to this strategy is to incorporate design for testability early in the design phase and to use a special architecture for a mixed-mode simu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluating VHDL-based ASIC synthesis tools

    Publication Year: 1992, Page(s):253 - 256
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    An evaluation of VHSIC hardware description language (VHDL) based design tools using synthesis vs. schematic capture-macrocell approach to field programmable gate array (FPGA) design is described. The risk of committing to an ASIC technology for a project that may or may not go into production can be mitigated by using FPGAs. Designing with VHDL allows flexibility if the decision is made to migrat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.2 μm CMOS differential I/O system capable of 400 Mbps transmission rates

    Publication Year: 1992, Page(s):427 - 431
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    High-bandwidth processor-to-processor connections, like the IEEE Std. 1596 scalable coherent interface (SCI), are being proposed as functional replacements for computer-system buses. To be cost-effective, it is important to drive the SCI links directly from CMOS VLSI components. To meet this need, a low-power, low-voltage-swing CMOS differential I/O driver/receiver system has been developed and is... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An ETL gate array implementation of a 2.5 Gb/s, 48-bit wide, channel programmable demultiplexer for fiber optic data transmission

    Publication Year: 1992, Page(s):91 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Describes unique circuit and logic design techniques in the implementation of a 48-channel programmable demultiplexer using a mature, high-yielding, bipolar ECL gate array for data transmission at 2.5 Gb/s. The new high-frequency macros and the unique design of the timing control circuitry enable a mature process technology to be used to more than double the operating rate of the technology compar... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A parallel BDD engine for logic verification

    Publication Year: 1992, Page(s):499 - 502
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    The use of binary decision diagrams (BDDs) for logic verification in a multiprocessing environment is described. A BDD engine, implemented as an array of transputers, is used as an accelerator for the NODEN suite of logic verification software. The efficiency of the parallel processing scheme was tested by constructing the BDD representation of a simple arithmetic logic unit (ALU) circuit View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using high level design models for generation of test vectors

    Publication Year: 1992, Page(s):345 - 348
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A description of a method using high-level design simulation that allows the use of functional timing simulations for test vector generation, while observing tester timing requirements is described. This method gives the designer the option of rapidly converting the design verification simulation modules in order to generate test vectors to the timing requirements of the targeted tester View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A minimal hardware overhead BIST data compaction scheme

    Publication Year: 1992, Page(s):368 - 371
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Existing data compaction schemes for built-in self-test (BIST) usually impose substantial hardware overhead. A minimal hardware overhead data compaction scheme is proposed that can achieve reasonably small aliasing with a hardware requirement as low as a one-stage linear feedback shift register (LFSR). Multiple signatures are checked, and all reference-signatures are made identical resulting in si... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automating circuit simulation and evaluation for the semi-custom IC design process

    Publication Year: 1992, Page(s):257 - 260
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    A data-driven software system called ASE (automatic simulation environment) that automatically creates, simulates, evaluates, and stores the results in a database is described. ASE significantly reduces the engineering design cycle time. By automating the creation and analysis of SPICE input and output files, this tool provides designers with more time to focus on designing and optimizing circuits... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 5 volt 0.5 μm mixed BiCMOS/CMOS channelless gate array

    Publication Year: 1992, Page(s):435 - 438
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A 0.5-μm BiCMOS/CMOS gate array that incorporates a new basic cell topology with an uneven mix of MOS and bipolar devices is described. This approach is aimed at maximizing the utilization of a BiCMOS gate array by enabling three kinds of macros to be implemented without any silicon penalty: low-power CMOS, high-drive CMOS, and BiCMOS. Fabricated with 0.5-μm BiCMOS technology, the 5-V gate a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ASIC technologies

    Publication Year: 1992, Page(s):97 - 106
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    The physical differences between currently available ASIC technologies are reported with emphasis on field-programmable gate arrays. Two factors affecting the choice of ASIC technology (costs and the importance of synthesis) are discussed. It is shown that the use of synthesis techniques can make as much difference in the performance of a system as a change in technology. The ability to use synthe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 3 volt ASIC macrocells for PC and controller applications

    Publication Year: 1992, Page(s):460 - 463
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A set of PC functions in the form of ASIC macrocells has been developed to help electronic system builders economically develop and offer battery-powered products. The new macrocells run at 2.7 V, as well as 5.5 V, and are compatible with AT&T's three standard-cell libraries in CMOS and BiCMOS View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high speed metal programmable static RAM compiler for 0.7 μm CMOS gate array

    Publication Year: 1992, Page(s):505 - 508
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    A static RAM compiler has been developed for a new 0.7 micron Leff CMOS gate array. The compiler is fully metal programmable and can compile RAMs from 8 bits to 64 K bits with typical access times of 4 ns to 10 ns, respectively. It supports partially decoded RAMs and variable aspect ratios. The compiler is well integrated into CAD tools View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Concurrent design of a chipset and its runtime environment

    Publication Year: 1992, Page(s):525 - 528
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    During the design of an accelerator board with two different ASICs, a methodology for the concurrent design of a chipset and a software system working as a runtime environment has been developed. The software system is implemented in the most appropriate language, e.g. C, and the board is modeled in a hardware description language, e.g. VHDL. A portable software library in C and VHDL was developed... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Grouping variables into multiport memories for ASIC data path synthesis

    Publication Year: 1992, Page(s):162 - 165
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    Grouping variables into multiport memories is an essential step for multiport memory based data path synthesis. The proposed system, GMD, not only groups variables into a minimum number of multiport memory modules, but also simultaneously minimizes the number of registers in each memory module. The minimization problem is formulated as a 0-1 integer linear programming (ILP) problem. Experiments on... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Designing programmable hearing aids using BiCMOS

    Publication Year: 1992, Page(s):411 - 414
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    BiCMOS is used for digitally programmable hearing aids. The analog signal processing function is implemented with bipolar circuits to provide amplification, automatic gain control (AGC), and filtering in the time-continuous domain, while digital logic and memory are implemented using standard cell CMOS. With on-chip chrome-silicon resistors and poly-to-p+ capacitors, a 17.8-mm2 View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testing gate-to-channel shorts in BiCMOS logic gates

    Publication Year: 1992, Page(s):351 - 354
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    The effects of gate to channel breakdown on the operation of BiCMOS logic gates are described. Both the static and dynamic behaviors of the gates are examined. The results of a SPICE simulation are presented. They show that gate to channel breakdown cannot be modeled by a stuck-at fault. Iddq and delay testings are effective in detecting these defects. Test patterns for I View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A methodology for automated behavioral verification of floating-point designs

    Publication Year: 1992, Page(s):487 - 490
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Behavioral verification of hardware designs confirms that the input/output relationship of the circuit agrees with its specification. This involves simulations of the circuits and the software code that models the hardware. Key issues in such simulations are the generation of test vectors and creation of models. A methodology that automates behavioral verification of floating-point (fp) designs is... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.