2013 NORCHIP

This paper presents the analysis of self-formation processes of micro and nanostructures in technologies of manufacturing high-speed semiconductor devices and integrated circuits (ICs) according possibilities to receive the minimal width of the base area and the methods used for the formation of contacts and electrodes. The results of the implementation of self-formation processes for creating new... View full abstract»

This work describes a simple process method for obtaining sub-micron and high aspect ratio lateral electrode gaps for rectangular plate micro-resonators and the resulting advantages. The structures are built of [110] single crystal silicon substrate by KOH etching, a novel combined two step oxidation processes and post-process electrostatic actuation method is proposed to achieve nearly smooth ver... View full abstract»

This paper proposes an analytical model describing the generation of switching current noise in CMOS substrates. The model eliminates the need for SPICE simulations in existing methods by conducting a transient analysis on a generic CMOS inverter and approximating the switching current waveform using a Modified Raised Cosine (MORAC) equation. The proposed model is scalable, easy to implement and c... View full abstract»

We propose a new methodology for Built-In Self-Test (BIST) where contrary to the traditional scan-path based logic BIST, the proposed solution for test generation does not need any additional hardware, and will not have any impact on the working performance of the system. A class of digital systems organized as pipe-lined signal processing architectures is targeted. The data used for processing in... View full abstract»

This paper presents and analyses several challenges of 3D volumetric display design process. Designs with video transfer and processing requires huge amounts of data bandwidth, thus most of the work is done with high-speed programmable logic chips. Introduction to volumetric technology is given and main design blocks and steps are explained. Results show that it is possible to implement all main b... View full abstract»

In this paper we present the results of a design-space exploration for a classification algorithm with respect to the inherent parallelism of the CoreVA CPU. The CoreVA is a configurable VLIW processor which has been mainly designed for energy-constrained applications. Energy-efficient signal-processing is essential for real-time applications on wireless body sensors (WBSs). Using a velocity-estim... View full abstract»

This paper presents an efficient envelope amplifier targeted to wideband Envelope Tracking (WBET) and wide-band Envelope Elimination and Restoration (EER). The design combines a Buck DC-DC converter with wideband operational amplifier. The goal is to achieve high operating frequency with good efficiency. The paper revisits some design features like the effect of slew rate limitation of switch curr... View full abstract»

This paper presents a integrated high voltage controller, which is fabricated in a 0.35pm high voltage CMOS technology(AMS H35), and can be applied in high voltage applications up to 115V. The high voltage output is controlled by 8-bit digital input code. In order to improve the accuracy and decrease the required area, it is implemented by a low voltage DAC and a high voltage amplifier for boostin... View full abstract»

This paper presents the design of a single stage dual-mode switched-capacitor (SC) capacitance-to-voltage converter (C2V) for the inkjet-printed capacitive humidity sensor. The specifications of C2V are optimized at the system level, emphasizing the C2V operation followed by the data converter. A closed form of the maximum output range of single stage C2V is given to avoid the cascade amplificatio... View full abstract»

Nanotechnology and Microsystems are having increasing impact on university curricula in electrical engineering. The advent of nanotechnology brings about new possibilities in nanoelectronics, including increasingly complex systems on chip, sophisticated technology fusion between electronic devices and non-electronic devices (such as bio-devices or chemical devices), and possibilities for developin... View full abstract»

One of the challenges in teaching integrated analog electronics is that it is difficult to offer courses where the students can design, layout and tape-out a circuit and subsequently perform measurements on the device due to the long turn-around time in IC fabrication. In this paper it is described how the sequences of courses in integrated analog electronics at the Technical University of Denmark... View full abstract»

This paper presents a detailed overview of the Micro- and Nano-electronics curriculum for Bachelor's and Master's degree studies programs in Vilnius Gediminas Technical University (VGTU). These programs focus on giving the ability and knowledge to students in designing an Integrated Circuits (ICs) using advanced EDA Tools. The Micro- and Nanoelectronics education programs cover all aspects of the ... View full abstract»

Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottle... View full abstract»

This paper presents a novel power amplifier (PA) architecture based on the combination of radio frequency pulse width modulation (RFPWM) and multilevel PWM. The architecture provides better dynamic range at high carrier frequency compared to RFPWM. The benefits of this architecture over multilevel PWM are that it only requires a single PA and no combiner. The average efficiency for an 802.11g base... View full abstract»

The feasibility of an integrated SiGe amplifier with 1 GHz band width and 30 dB gain for cryogenic temperatures has been studied. The standard models do not simulate special low temperature phenomena and give erroneous results below 50 K. We have circumvented this problem by using an experimentally defined “effective temperature” in simulations. Thereafter we have studied a cascade a... View full abstract»

This paper concentrates on finding optimal yet simple predistorter for an amplifier in envelope tracking (ET) system. The scope is to linearize AM-AM error statically by maintaining constant compression by polynomial fit to the envelope path. For static AM-PM predistortion, the path delay between RF and envelope paths is fixed. A set complex memory predistorters were also tested and compared to th... View full abstract»

Impedance matching is present in every radio frequency (RF) integrated circuit (IC). Matching networks are implemented in receiver, transmitter and inter-stage circuits. At lower carrier frequencies the significance of impedance matching networks is far less than at higher frequencies. As modern RF systems tend to employ higher carrier frequencies, the topic of impedance matching becomes more and ... View full abstract»

In this paper, a fault tolerant method is proposed for application specific Network on Chip. The goal of this paper is to determine a replacement path when faults occur on network links. Selecting criteria for the replacement path is choosing minimal path with the least congestion. In the proposed method, a decision tree structure is employed and a method for calculating Network on Chip reliabilit... View full abstract»

Self-heating has already been proven to be one of the key sources to memory effects in RF power amplifiers (PAs). However, mechanisms behind the generation of memory effects, as caused by self-heating have not been well documented. On basis of transistor physical properties this paper proposes a simple electro-thermal model and shows how self-heating can generate different types of memory effects,... View full abstract»

A triple cascaded current-reuse CMOS low noise amplifier (LNA) for 3.5 GHz WiMAX application is presented. Three common-source amplifiers are stacked and reuse the same current. This triple cascaded topology is able to enhance power gain but needs two coupling networks which costs enormous chip size. In order to have reasonable chip size, two coupling methods are investigated. To achieve input and... View full abstract»

Nowadays envelope tracking (ET) is considered one of the most appealing techniques for the efficiency enhancement of RF power amplifiers (PAs), but it also introduces a number of additional challenges for the system simulation and implementation. In this context, this paper aims to provide a new behavioral model capable of an improved performance when used for the modeling and predistortion of RF ... View full abstract»

This paper presents an architecture for a SiGe E-band power amplifier using a stacked transformers for output power combination. According to simulations, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better compared to a single common 2:1 transformer with two turns on the secondary side. The power combination allows for a lo... View full abstract»