# Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

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• ### Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

Publication Year: 1999
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Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the ori... View full abstract»

• ### Author index

Publication Year: 1999, Page(s): 302
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• ### Arithmetic circuits for analog digits

Publication Year: 1999, Page(s):186 - 191
Cited by:  Papers (9)
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The Overlap Resolution Number System (ORNS) employs bit level analog residue arithmetic, and opens up a powerful approach to digital computing. This new redundant representation of signals, with Continuous Valued Digits, presents new methods for binary arithmetic and digital signal processing. The number system is based on analog residue digits, as opposed to binary or multiple-valued digit levels... View full abstract»

• ### Down literal circuit with neuron-MOS transistors and its applications

Publication Year: 1999, Page(s):180 - 185
Cited by:  Papers (8)  |  Patents (1)
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A voltage-mode neuron-MOS(νMOS) down literal circuit which realizes an arbitrary down literal function is proposed. It provides the benefit that the circuit can be easily fabricated by standard CMOS process, instead of the multi-level ion implantation applied in the conventional circuit. It has a variable threshold voltage by way of controlling only two bias voltages. Its noise margin and switc... View full abstract»

• ### Ternary multiplication circuits using 4-input adder cells and carry look-ahead

Publication Year: 1999, Page(s):174 - 179
Cited by:  Papers (3)
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We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary multiplication. One advantage of the ternary adder is that four instead of three inputs within a binary representation will be summed up. In this paper we will compare the complexity of binary against ternary multipliers. ... View full abstract»

• ### Multiple-valued content-addressable memory using metal-ferroelectric-semiconductor FETs

Publication Year: 1999, Page(s):30 - 35
Cited by:  Papers (5)
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This paper presents a design of a non-volatile multiple-valued content-addressable memory (MVCAM) using metal-ferroelectric-semiconductor (MFS) FETs. An MFSFET is an important device with a non-destructive read scheme. Multiple-valued stored data are directly represented by remnant polarization states that correspond to threshold voltages of an MFSFET. Since one-digit comparison between multiple-v... View full abstract»

• ### Bi-decompositions of multi-valued functions for circuit design and data mining applications

Publication Year: 1999, Page(s):50 - 58
Cited by:  Papers (4)
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We present efficient algorithms for the bi-decomposition of arbitrary incompletely specified functions in variable-valued logic. Several special cases are discussed. The algorithms are especially applicable for Data Mining applications, because, in contrast to the general multi-valued approaches to function decomposition that decompose to arbitrary tables, we create a network from multi-valued two... View full abstract»

• ### Shared multiple-valued decision diagrams for multiple-output functions

Publication Year: 1999, Page(s):166 - 172
Cited by:  Papers (2)
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In this paper, we propose a method to represent multiple-output functions using shared multiple-valued decision diagrams (SMDDs). We show an algorithm for pairing the input variables of binary decision diagrams (BDDs). We also present the pair sifting that moves pairs of 4-valued input variables to speed up the normal sifting, and to produce compact SMDDs. The size of the SMDD is the total number ... View full abstract»

• ### Self-checking multiple-valued circuit based on dual-rail current-mode differential logic

Publication Year: 1999, Page(s):275 - 279
Cited by:  Papers (1)
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A multiple-valued current-mode (MVCM) circuit based on dual-rail differential logic has been proposed for high-speed arithmetic systems at a low supply voltage. This paper presents a new totally self-checking circuit based on dual-rail MVCM logic, where almost all the basic components except a differential-pair circuit have been already duplicated which results in small hardware overhead compared ... View full abstract»

• ### Evaluation of m-valued fixed polarity generalizations of Reed-Muller canonical form

Publication Year: 1999, Page(s):92 - 98
Cited by:  Papers (1)
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This paper compares the complexity of three different fixed polarity generalizations of Reed-Muller canonical form to multiple-valued logic. The Galois field-based expansion introduced by D.H. Green and I.S. Taylor (1974), the Reed-Muller-Fourier form of R.S. Stankovic and C. Moraga (1998), and the expansion over addition modulo m, minimum and the set of all literal operators introduced by the aut... View full abstract»

• ### B-ternary logic based asynchronous micropipeline

Publication Year: 1999, Page(s):214 - 219
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In this paper, a B-ternary logic based asynchronous pipeline is presented. The pipeline processes binary dates elastically. It has high speed operation potential an spite of having an idle phase, because the stages of the pipeline operate concurrently. The mechanism for correct pipeline behavior and the designed circuits are provided View full abstract»

• ### On axiomatization of conditional entropy of functions between finite sets

Publication Year: 1999, Page(s):24 - 28
Cited by:  Papers (3)
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In this paper we present a new axiomatization of the notion of entropy of functions between finite sets and we introduce and axiomatize the notion of conditional entropy between functions. The results can be directly applied to logic functions, which can be regarded as functions between finite sets. Our axiomatizations are based on properties of entropy with regard to operations commonly applied t... View full abstract»

• ### Structural and behavioral modeling with monadic logics

Publication Year: 1999, Page(s):142 - 151
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Logic offers the possibility of modeling and reasoning about hardware and software. But which logic? We propose monadic logics of strings and trees as good candidates for many kinds of discrete systems. These logics are natural, decidable, yet substantially more expressive, extensions of Boolean logic. We motivate their applicability through examples View full abstract»

• ### Supplementary symmetrical logic circuit structure

Publication Year: 1999, Page(s):42 - 47
Cited by:  Papers (5)
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The Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) is a fully active, self sustaining architecture intended primarily for the design and fabrication of logic synthesizing circuits with a radix greater than two. Any r'-valued logic function of n'-places (where: r' is the radix and an integer greater than I, and n' is an integer greater than 0) can be implemented with the SUS-LOC st... View full abstract»

• ### Information relationships and measures in application to logic design

Publication Year: 1999, Page(s):228 - 235
Cited by:  Papers (7)
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In this paper, the theory of information relationships and relationship measures is considered and its application to logic design is discussed. This theory makes operational the famous theory of partitions and set systems of Hartmanis. The information relationships and measures enable us to analyze relationships between the modeled information streams and constitute an important analysis apparatu... View full abstract»

• ### Synthesis of multiple-valued decision diagrams using current-mode CMOS circuits

Publication Year: 1999, Page(s):160 - 165
Cited by:  Papers (2)
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In this paper, an algorithm for generating modular designs of Ordered Multiple Decision Diagrams (OMDDs) for Current-Mode CMOS Logic (CMCL) implementation is introduced. The OMDD structures for a set of twelve benchmark circuits from the LGSynth93 using radices ranging from r=2 to r=10 are generated and compared in terms of size and speed. It is observed that MODDs with radices r∈(2, 4, 8) re... View full abstract»

• ### Representation theorems and theorem proving in non-classical logics

Publication Year: 1999, Page(s):242 - 247
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In this paper we present a method for automated theorem proving in non-classical logics having as algebraic models bounded distributive lattices with certain types of operators. The idea is to use a Priestley-style representation for distributive lattices with operators in order to define a class of Kripke-style models with respect to which the logic is sound and complete. If this class of Kripke-... View full abstract»

• ### Semirigidity problems in k-valued logic

Publication Year: 1999, Page(s):256 - 260
Cited by:  Papers (2)
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The study of semirigid sets arose from the classification of bases. In this complex problem-fully solved only for |A|=2, 3-one of the task is to find all minimal nontrivial intersections of systems of maximal clones. Most of the clones are determined by reflexive relations (binary or of higher arities) and so we need to determine subsets R of these relations such that every function preserving all... View full abstract»

• ### Highly testable Boolean ring logic circuits

Publication Year: 1999, Page(s):268 - 274
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In this paper we show how Boolean Ring logic, a group-based logic, leads to a circuit implementation that is highly testable. We develop Boolean Ring based expressions, which we call Generalized-Literal Boolean-Ring Sum-of-Products (GL-BRSOP) and Universal-Literal Boolean-Ring Sum-of-Products (UL-BRSOP) to represent (powers of 2)-valued MVL functions. Our BRSOPs: allow MVL functions to be implemen... View full abstract»

• ### Partial clones and their generating sets

Publication Year: 1999, Page(s):85 - 90
Cited by:  Papers (6)
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We present some of our recent results on partial clones. Let A be a non singleton finite set. For every maximal clone C on A, we find the maximal partial clone on A that contains C. We also construct families of finitely generated maximal partial clones as well as a family of not finitely generated maximal partial clones on A. Furthermore, we study the pairwise intersections of all maximal partial... View full abstract»

• ### On the number of multilinear partitions and the computing capacity of multiple-valued multiple-threshold perceptrons

Publication Year: 1999, Page(s):208 - 213
Cited by:  Papers (3)
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We introduce the concept of multilinear partition of a point set V⊂Rn and the concept of multilinear separability of a function f:V→K={0, ..., k-1}. Based on well known relationships between linear partitions and minimal pairs, we derive formulae for the number of multilinear partitions of a point set in general position and of the set K2. The (n, k, s)-perceptrons p... View full abstract»

• ### Quaternion groups versus dyadic groups in representations and processing of switching functions

Publication Year: 1999, Page(s):18 - 23
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In this paper we compare effects of two different domain groups for switching functions to the efficiency of calculation of spectral transforms (ST) representations and the complexity of Decision diagrams (DDs) representations. Dyadic groups and quaternion groups are assumed for domain groups for switching functions. We compared space and time complexity in calculation of STs representations throu... View full abstract»

• ### Gigantic pairs of minimal clones

Publication Year: 1999, Page(s):74 - 79
Cited by:  Papers (4)
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L. Szabo (1992) asked for the minimal number n=n(|A|) such that the clone of all operations on A can be generated as the join of n minimal clones. He showed, e.g., n(p)=2 for any prime p, and later G. Czedli (1998) proved that if k has a divisor ⩾5 then n(k)=2. In this paper, a pair (f, g) of operations is called gigantic if each of f and g generates a minimal clone and the set {f, g} generate... View full abstract»

• ### From a fuzzy flip-flop to a MVL flip-flop

Publication Year: 1999, Page(s):294 - 299
Cited by:  Papers (1)
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The paper presents a circuit description of a MVL flip-flop which is implemented in MOS technology. The circuit has its origins in a bipolar implementation of a fuzzy flip-flop. The proposed circuit not only simplifies the original bipolar design but it offers considerable potential for a VLSI implementation. Simulation of the circuit using HSpice indicates that it can also be interpreted as a mul... View full abstract»

• ### Research on the similarity among precomplete sets preserving m-ary relations in partial k-valued logic

Publication Year: 1999, Page(s):136 - 139
Cited by:  Papers (1)
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In multiple-valued logic theories, the characterization of Sheffer functions is an important problem, it includes the decision and construction for Sheffer functions in Pk and Pk*. The solution of these problems depends on the solution of the decision problem for completeness in Pk and Pk*, and reduced to determining the minimal coverings of precomplete ... View full abstract»