Proceedings Ninth Great Lakes Symposium on VLSI

4-6 March 1999

Filter Results

Displaying Results 1 - 25 of 105
  • Proceedings Ninth Great Lakes Symposium on VLSI

    Publication Year: 1999
    Request permission for commercial reuse | PDF file iconPDF (569 KB)
    Freely Available from IEEE
  • Why is time-varying control necessary for signal processing with locally-connected quantum-dot arrays?

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5 KB)

    Summary form only given, as follows. New nanodevices which encode information into the geometrical charge distribution of artificial (or natural) molecules have been proposed. Functional units are composed by exploiting the electrostatic coupling between neighboring devices. In these units, processing takes place by reshaping the electron density of the molecules, and not by switching electron cur... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author index

    Publication Year: 1999, Page(s):397 - 400
    Request permission for commercial reuse | PDF file iconPDF (450 KB)
    Freely Available from IEEE
  • A VLSI architecture for ATM algorithm-agile encryption

    Publication Year: 1999, Page(s):325 - 328
    Cited by:  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    In this paper a VLSI architecture is proposed for an algorithm-agile encryptor for ATM networks. The architecture is based on a circular sorting queue that buffers and switches incoming cells to the appropriate encryption pipelines. It also handles multicast cells that require different encryption algorithms for different destinations. Delay and loss priority are analyzed for multi-class traffic p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low power techniques for digital GaAs VLSI

    Publication Year: 1999, Page(s):321 - 324
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    This paper presents a survey of low-power digital Gallium Arsenide logic applicable to high performance VLSI circuits and systems and proposes new design concepts in methodology and architecture based on the implementation of Pseudo-Dynamic Latched Logic in order to achieve reasonable power-delay-area tradeoff. The approach is highly suitable for self-timed systems where the complexities of clock ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accurate resource estimation algorithms for behavioral synthesis

    Publication Year: 1999, Page(s):338 - 339
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Given a scheduled data flow graph the functional, storage, and interconnect (multiplexors) resources are analytically estimated taking into account the effects of post-scheduling tasks. Complexity of the controller implementation is also estimated. The novelty of this work lies in predicting the effects of the post-scheduling task on the final amount of resources, the effects of data path resource... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An all digital BiCMOS phase lock loop for VLSI processors

    Publication Year: 1999, Page(s):318 - 320
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    A BiCMOS all digital phase lock loop is described. This design is suitable for applications such as clock recovery and frequency synthesis in VLSI processors where thermal stability is an important factor. The main block of the design consists of a digitally controlled oscillator with wide frequency range and high thermal stability compared to CMOS design. An improved BiCMOS adder/subtractor was a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A bandpass sigma-delta for software low-power and low-voltage radio by using PATH technique

    Publication Year: 1999, Page(s):198 - 201
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    This paper proposes a PArallel Two patH (PATH) technique for oversampled bandpass analog-to-digital converter in low-power and low-voltage environment to relax the settling requirement and to increase signal-to-noise ratio. The design considerations for the implementation are evaluated and strategies overcome the possible problems. It is clocked at 20 MHz and digitized a 200 kHz bandwidth signal c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Proposal of data-driven processor architecture Qv-K1

    Publication Year: 1999, Page(s):336 - 337
    Cited by:  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB)

    This paper presents an extended SIMD form data operation for multi-media signal processing and a performance evaluation of data-driven processor Qv-K1. By appending proposed data-parallel operation mechanism, the number of executed instructions is reduced compared to SIMD. The processing ability of this processor could be increased View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel high-speed flip-flop circuit using RTDs and HEMTs

    Publication Year: 1999, Page(s):154 - 157
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    An RTD (resonant tunneling diode)-based flip-flop circuit with a new configuration is proposed. The circuit features an SCFL interface for both input and output, and achieves high-speed operation with a simplified configuration. The circuit consists of only two RTDs and three HEMTs, and works as a delayed flip-flop (D-FF) with return-to-zero (RZ) mode output. 50 Gbit/s operation is confirmed by SP... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An integrated approach for synthesizing LUT networks

    Publication Year: 1999, Page(s):136 - 139
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    This paper presents a method for synthesizing lookup table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods; many decomposition methods that are not only algebraic but also functional are integrated. Our method can be thought of as a general framework for LUT network synthesis integrating various decomposition methods. The experimental r... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise immunity of digital circuits in mixed-signal smart power systems

    Publication Year: 1999, Page(s):314 - 317
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    Experimental data describing circuit and physical design issues that influence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The principal result of this paper is the characterization of the conditions under which substrate noise generated by high power analog circuitry affects digital latches. The experimental data characterize a variety o... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A methodology for minimizing power dissipation of embedded systems through hardware/software partitioning

    Publication Year: 1999, Page(s):86 - 89
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    We present a novel approach that minimizes the power dissipation of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping clusters of operations/instructions to a core that yields a high utilization rate of the involved resources (ALUs, multipliers, shifters etc.) and thus minimizing power dissipation. Our approach is comprehensive since i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Methodology of logic synthesis for implementation using heterogeneous LUT FPGAs

    Publication Year: 1999, Page(s):242 - 243
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    Logic synthesis method for heterogeneous LUT FPGAs implementation is proposed As all example, XILINX4000 architecture is considered. The method takes XILINX4000 architectural features (heterogeneous LUTs of 3 and 4 inputs) into account and includes two step decomposition. In the first step, two-level logic representation is transformed into a graph of at most 4 fanin nodes (after this step, each n... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficiently searching the optimal design space

    Publication Year: 1999, Page(s):192 - 195
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    One of the primary advantages of a high-level synthesis system is its ability to explore the design space. This paper presents several methodologies for design space exploration that compute all optimal tradeoff points for the combined problem of scheduling, clock length determination, and module selection. We discuss how each methodology takes advantage of both the structure within the design spa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low power design of an acoustic echo canceller Gmdfα algorithm on dedicated VLSI architectures

    Publication Year: 1999, Page(s):334 - 335
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (28 KB)

    The acoustic echo cancellation with adaptive filters is a computationally intensive problem that needs real time cost effective solutions for embedded systems. Low power optimized signal processing architectures are likely to provide such solutions in the future. In this paper, we present different real-time optimized architectures of the popular Gmdfα algorithm, obtained by an HLS CAD tool ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A memory design in QCAs using the SQUARES formalism

    Publication Year: 1999, Page(s):166 - 169
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    We present a formalism for implementing circuits with quantum-dot cellular automata (QCA), comprising a set of standard circuit elements with uniform layout rules. The formalism simplifies circuit design from an engineering perspective and overcomes an observed sensitivity of QCA systems to input delays. A design for an addressable shift register is implemented, and promises considerable density g... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ultrahigh-speed circuits using resonant tunneling devices

    Publication Year: 1999, Page(s):150 - 153
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    Ultrahigh-speed circuit applications of resonant tunneling diodes (RTDs) have been developed. One of the key concepts is the merged utilization of RTDs and high electron mobility transistors (HEMTs). The integration technology for InP-based RTDs and HEMTs has been developed. Another key technology developed is a circuit configuration using series-connected RTDs, driven by a clocked bias, in combin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A greedy router with technology targetable output

    Publication Year: 1999, Page(s):252 - 255
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    Our objective was to integrate an effective channel routing algorithm with the Chip Design Language (CDL) algorithmic layout tool. CDL uses technology targetable layout techniques, so that the output of the routing algorithm can easily be ported to different technologies. We introduce the technology independent features of CDL and describe how a greedy router can be interfaced to it. Specific feat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reducing BDD size by exploiting structural connectivity

    Publication Year: 1999, Page(s):132 - 135
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    Computer-aided design tools have been limited by the use of the Binary Decision Diagram (BDD). The major drawback of the BDD is its abundant usage of CPU time and memory. Techniques such as BDD variable ordering and sharing have been used in the past to address the size issue. However these techniques remain to be limited to modest-sized circuits. In this paper, we present a significant variation ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Congestion mitigation during placement

    Publication Year: 1999, Page(s):228 - 229
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    High post-placement congestion in complex ASICs and microprocessors may pose severe constraints on the wiring resources, thereby causing wireability, timing and noise problems. Linear wirelength-based mincut partitioning algorithms have some built-in advantages for reducing congestion. We present a mathematical model of congestion and experimentally investigate various congestion mitigation techni... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Self-checking of FPGA-based control units

    Publication Year: 1999, Page(s):292 - 295
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The paper introduces a new technique for on-line checking of FPGA based Control Units (CUs). This technique is based on the architecture comprising two portions. A self-checking CU and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an Evolution block and an Execution block. Comparison of code vectors being transferred between the blocks of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • NMOS energy recovery logic

    Publication Year: 1999, Page(s):310 - 313
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    In this paper, we describe NMOS Energy Recovery Logic (NERL) which exhibits high throughput with low energy consumption due to efficient energy transfer and recovery using adiabatic and bootstrapping techniques. NERL shows full output voltage swing, insensitivity to output load capacitance, less dependency on power-clock frequency and complementary outputs for balanced capacitance load to power-cl... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New 2 Gbit/s CMOS I/O pads

    Publication Year: 1999, Page(s):82 - 85
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    A couple of low complexity high performance input and output pads are proposed: they have been designed in 0.7 μm CMOS ES2 technology and support bit rates ranging from DC up to 2 Gbit/s. The differential input pad and the differential output pad interface true PECL external logic levels to full swing 5 V CMOS internal levels View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A multiple-input single-phase clock flip-flop family

    Publication Year: 1999, Page(s):240 - 241
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (28 KB)

    The design of a versatile CMOS semi-static true singlephase clock flip-flop family is presented. It naturally supports multiple, multiplexed, inputs. Asynchronous Set/Reset are easily implemented. Switching power is lower than for some other semi-static flip-flop techniques View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.