2011 Asian Test Symposium

Shrinking timing margins for modern high speed digital circuits require a careful reconsideration of faults and fault models. In this paper, we discuss detection of transition faults in the presence of small clock delay faults. We first show that in the presence of a delay fault on a clock line some transition faults may fail to be detected. We propose a test generation method for detecting such f... View full abstract»

Manufacturing test for clock-domain crossing(CDC) defects is a major challenge for multi-core system-on chip(SoC) designs in the nanometer regime. Setup- and hold time violations in flip-flops situated on clock boundaries may lead to catastrophic failures, even when circuits are equipped with synchronizers at clock boundaries. In this work, we comprehensively study the effect of CDC faults, and pr... View full abstract»

Memory interface speed has been rapidly increasing to overcome the performance gaps between microprocessor and memory. Testing the I/O timing parameters at-speed has become a challenge because of the limitations on the test clock frequencies provided by low-cost testers. This paper presents a technique to generate a dual-capture signal with a programmable delay for both rising and falling transiti... View full abstract»

High speed signal acquisition and characterization contributes a significant amount to the total test cost of the finished product in modern high speed systems. Incoherent under-sampling allows robust and low cost signal acquisition without requiring a prior accurate knowledge of signal period. In this paper we propose a frequency estimation and signal reconstruction technique for incoherently sub... View full abstract»

Recent research has shown that some defects are detect resilient under normal or high temperature, therefore tests for those defects must be applied under lower temperature. On the other hand, some tests need to be applied under high temperature to improve the detection sensitivity. Thus temperature dependent testing which applies tests at different temperature ranges is needed. This paper discuss... View full abstract»

In order to provide high performance with low power consumption, modern multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage settings. Effective defect screening for the embedded cores in such multicore chips requires test application at their different operating voltages, which leads to higher test time and test cost. We propose a fast h... View full abstract»

A new test application scheme is proposed for low-power scan testing, which is able to compress test data significantly. A combination of a scan architecture and an existent test compression scheme can compress test data even better. Test power can be reduced greatly based on the new test application scheme, according to which only a subset of scan flip-flops shifts a test vector or captures test ... View full abstract»

Test data decompressors targeting low power scan testing introduce significant amount of correlation in the test data and thus they tend to adversely affect the coverage of unmodeled defects. In addition, low power decompression needs additional control data which increase the overall volume of test data to be encoded and inevitably increase the volume of compressed test data. In this paper we sho... View full abstract»

Field test for reliability is usually performed with small amount of memory resource, and it requires a new technique which might be somewhat different from the conventional manufacturing tests. This paper proposes a novel technique that improves fault coverage or reduces the number of test vectors that is needed for achieving the given fault coverage on scan-based BIST structure. We evaluate a mu... View full abstract»

Scan test is the standard method, practiced by industry, that has consistently provided high fault coverage due to high controllability and high observability. The scan chain allows to control and observe the internal signals of a chip. However, this property also facilitates hackers to use scan architecture as a means to breach chip security. This paper addresses this issue by proposing a new met... View full abstract»

While raising the level of abstraction in design methodologies is uniformly accepted as desirable, raising Design For Test of complex VLSI chips is still challenging for both analysis and implementation. Still, testing logic can be described at the RT-level, and inserting it before synthesis has many advantages, among which the ability to debug testability issues early in the design flow, and leve... View full abstract»

Test and testability are essential concerns for design in any abstraction level, and are even more challenging for high level designs. Because of complexity of today's designs, design at ESL (electronic system level) using transaction level modeling (TLM) has become a focal point of today's system level designers. However, there are no standard test methods or conventions proposed for this level o... View full abstract»

Shrinking feature sizes have magnified deep sub-micron effects, resulting in integrated circuits prone to timing-related defects. Stringent test quality requirements have therefore mandated the use of at-speed testing schemes, however, excessive switching activity during the launch operation may result in yield loss. In this paper, we propose a design partitioning technique that can reduce power d... View full abstract»

This paper discusses a low-power test scheme compatible with both test compression and built-in self-test environments. The key contribution is a detailed analysis showing that a simple power-aware controller may allow significant reductions of toggling rates when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifi... View full abstract»