Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

21-21 Jan. 1999

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  • Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

    Publication Year: 1999
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    Freely Available from IEEE
  • Crosstalk reduction by transistor sizing

    Publication Year: 1999, Page(s):137 - 140 vol.1
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB)

    In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and validated by experiments. Then transistor sizing for timing and noise is discussed and solved using optimization techniques. Experimental results suggest that crosstalk violations can be removed by transistor sizing with very s... View full abstract»

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  • Author index

    Publication Year: 1999, Page(s):367 - 370
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    Freely Available from IEEE
  • Embedded tutorial: hardware/software codesign

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (49 KB)

    Due to the advance of VLSI technology, it is now possible to fabricate very complicated systems on a chip, which includes CPUs, peripheral circuits, and on-chip memories. These kinds of chips are very effective to implement various electronic systems such as for multimedia processing, communication, and real-time control. However there is a serious problem, called "design productivity crisis", to ... View full abstract»

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  • Supplement to the Proceeding of Asia and South Pacific Design Automation Conference 1999

    Publication Year: 1999, Page(s): 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    First Page of the Article
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  • FSM modeling of synchronous VHDL design for symbolic model checking

    Publication Year: 1999, Page(s):363 - 366 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    In this paper, we defined a new FSM model based on the synchronous behavior and symbolic representation technique. The algorithm to elaborate the model from the VHDL description of synchronous circuits is presented. By eliminating the unnecessary transition function, our model has much less states than Deharbe's mixed model. The experimental results demonstrate the model and modeling method can ma... View full abstract»

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  • Timing-driven bipartitioning with replication using iterative quadratic programming

    Publication Year: 1999, Page(s):105 - 108 vol.1
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    We present an algorithm for solving a general min-cut, two-way partitioning problem subject to timing constraints. The problem is formulated as a constrained programming problem and solved in two phases: cut-set minimization and timing satisfaction. A mathematical programming technique based on iterative quadratic programming (TPIQ) is used to find an approximate solution to the constrained proble... View full abstract»

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  • A method for evaluating upper bound of simultaneous switching gates using circuit partition

    Publication Year: 1999, Page(s):291 - 294 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. In order to increase the accuracy, we adopted an evaluation function that takes account of both the interco... View full abstract»

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  • Fast Boolean matching under permutation using representative

    Publication Year: 1999, Page(s):359 - 362 vol.1
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As a basis of the Boolean matching, we use the notion P-representative. If two functions have the same P-representative then they match. We develop a breadth-first search technique to quickly compute the P-representative. On an... View full abstract»

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  • Node sampling technique to speed up probability-based power estimation methods

    Publication Year: 1999, Page(s):157 - 160 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimate the power consumption of a circuit. It is different from the previous speed-up techniques for probability-based methods in that the previous techniques reduce the processing time for each node while our method reduces t... View full abstract»

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  • The design of delay insensitive asynchronous 16-bit microprocessor

    Publication Year: 1999, Page(s):33 - 36 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Recently, asynchronous design has resurged to exploit potential advantages of asynchronous VLSI such as; high-performance, low power consumption, timing fault tolerance and design cost reduction. This paper describes our first design and implementation of the DINAMIK project which aims to show realizability of potential merits of asynchronous VLSI and to establish the design methodology. In the de... View full abstract»

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  • Design re-use: where is the productivity going to come from?

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Semiconductor process geometries are shrinking and the available silicon capacity is growing at an amazing pace. Consumerization and convergence applications are causing tremendous time to market pressures, resulting in increased product complexity and reduced design cycle times. The gap between what can be built (silicon capacity) and what can be designed is widening. This `design productivity ga... View full abstract»

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  • Low power CMOS off-chip drivers with slew-rate difference

    Publication Year: 1999, Page(s):169 - 172 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    This paper proposes an approach to reduce the short circuit current of CMOS off-chip drivers by individually controlling the input slew rates to the P and N channel transistors that drive the output pad. The slew rates are deliberately designed such that the N(P) transistor at the output stage will be turned off faster than the P(N) transistor is turned on for low-to-high (high-to-low) output tran... View full abstract»

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  • An efficient iterative improvement technique for VLSI circuit partitioning using hybrid bucket structures

    Publication Year: 1999, Page(s):73 - 76 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    In this paper, we present a fast and efficient iterative improvement partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to their time efficiency, IIP algorithms are widely used in VLSI circuit partitioning. As the performance of these algorithms depends on choices of moving cells, various such methods have been proposed. In particular, the cluste... View full abstract»

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  • An analytical delay model for SRAM-based FPGA interconnections

    Publication Year: 1999, Page(s):101 - 104 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    In an SRAM-based FPGA, MOS transistors connect wire segments to construct interconnections between CLBs, resulting in large and unpredictable path delays. So it is necessary to be able to estimate interconnection delays quickly and accurately in order that performance-driven layout and analysis algorithms can achieve high quality. Because the effective channel resistance of a MOS transistor change... View full abstract»

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  • An adaptive BIST to detect multiple stuck-open faults in CMOS circuits

    Publication Year: 1999, Page(s):287 - 290 vol.1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of single-input-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average le... View full abstract»

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  • A new global routing algorithm independent of net ordering

    Publication Year: 1999, Page(s):245 - 248 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    We proposed a new global routing algorithm solving the net ordering problem. The algorithm uses random optimization methods to keep the equality of earlier routed nets and later routed nets in passing congested areas. It can find a solution independent of net ordering in short time. A global router is implemented in this method. Experiments show that the router performs much faster than Matula rou... View full abstract»

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  • A genetic algorithm based approach for multi-objective data-flow graph optimization

    Publication Year: 1999, Page(s):355 - 358 vol.1
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    This paper presents a genetic algorithm based approach for algebraic optimization of behavioral system specifications. We introduce a chromosomal representation of data-flow graphs (DFG) which ensures that the correctness of algebraic transformations realized by the underlying genetic operators selection, recombination, and mutation is always preserved. We present substantial fitness functions for... View full abstract»

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  • Application driven variable reordering and an example implementation in reachability analysis

    Publication Year: 1999, Page(s):327 - 330 vol.1
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Variable reordering is the main approach to minimize the size of Ordered Binary Decision Diagrams. But despite the huge effort spent, up to now, to design different reordering heuristics, their performance often does not meet the needs of the applications. In many OBDD-based computations, the time cost for reordering dominates the time spent by the computation itself. There are some known approach... View full abstract»

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  • Automatic constraint transformation with integrated parameter space exploration in analog system synthesis

    Publication Year: 1999, Page(s):153 - 156 vol.1
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be confined to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher lev... View full abstract»

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  • Waveform relaxation of linear integral-differential equations for circuit simulation

    Publication Year: 1999, Page(s):61 - 64 vol.1
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    We present waveform relaxation of linear integral-differential equations which occur in circuit simulation. We give sufficient conditions for convergence and numerical experiments to verify the theoretical results View full abstract»

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  • A 10 b 58 MHz CMOS A/D converter for high-speed video applications

    Publication Year: 1999, Page(s):29 - 32 vol.1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    This paper describes a 10 b 50 MHz CMOS ADC for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a power reduction technique for high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in... View full abstract»

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  • Interconnect delay estimation models for synthesis and design planning

    Publication Year: 1999, Page(s):97 - 100 vol.1
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    In this paper we develop a set of interconnect delay estimation models with consideration of various layout optimizations, including optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous buffer insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90% accuracy on average compared with those fr... View full abstract»

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  • Chip-package codesign-challenges and directions

    Publication Year: 1999
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB)

    Increasingly the package, and associated discretes, contribute critically to the overall circuit performance, rather than just providing a connection function. These performance issues are critical today and are fast becoming more complex than current CAD tool trends will be able to support. For example, in today's digital systems, the package design is an important part of the signal integrity eq... View full abstract»

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  • Roadmap organization and activities in Japan

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    Describes the “technical difficulties to be solved and future technical directions” in various semiconductor technology areas. This activity is meaningful not only for semiconductor vendors but also for related industries, academia and research laboratories. In December 1998, STRJ (Semiconductor Technology Roadmap Committee of Japan) was established under EIAJ (Electronics Industry Ass... View full abstract»

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