2011 International Conference on Parallel Processing

13-16 Sept. 2011

Filter Results

Displaying Results 1 - 25 of 94
  • [Front cover]

    Publication Year: 2011, Page(s): C1
    Request permission for reuse | PDF file iconPDF (135 KB)
    Freely Available from IEEE
  • [Title page i]

    Publication Year: 2011, Page(s): i
    Request permission for reuse | PDF file iconPDF (26 KB)
    Freely Available from IEEE
  • [Title page iii]

    Publication Year: 2011, Page(s): iii
    Request permission for reuse | PDF file iconPDF (131 KB)
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2011, Page(s): iv
    Request permission for reuse | PDF file iconPDF (168 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2011, Page(s):v - xi
    Request permission for reuse | PDF file iconPDF (161 KB)
    Freely Available from IEEE
  • Welcome message from the Chairs

    Publication Year: 2011, Page(s): xii
    Request permission for reuse | PDF file iconPDF (98 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2011, Page(s):xiii - xiv
    Request permission for reuse | PDF file iconPDF (114 KB)
    Freely Available from IEEE
  • Program Committee

    Publication Year: 2011, Page(s):xv - xvii
    Request permission for reuse | PDF file iconPDF (122 KB)
    Freely Available from IEEE
  • Reviewers

    Publication Year: 2011, Page(s):xviii - xxi
    Request permission for reuse | PDF file iconPDF (86 KB)
    Freely Available from IEEE
  • Keynotes

    Publication Year: 2011, Page(s):xxii - xxvi
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    Provides an abstract for each of the keynote presentations and may include a brief professional biography of each View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Panel session: Programming Environments at Extreme Scale

    Publication Year: 2011, Page(s): xxvii
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (90 KB)

    Summary form only given, as follows. Exa-scale systems are expected to present an extremely large challenge to computational scientists attempting to leverage the full extent of the capabilities such systems will provide. The systems are expected to have on the order of ten million computational elements, with more than several-hundred such cores per node, include multiple types of computational e... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A DFA with Extended Character-Set for Fast Deep Packet Inspection

    Publication Year: 2011, Page(s):1 - 10
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    Deep packet inspection (DPI), based on regular expressions, is expressive, compact, and efficient in specifying attack signatures. We focus on their implementations based on general-purpose processors that are cost-effective and flexible to update. In this paper, we propose a novel solution, called deterministic finite automata with extended character-set (DFA/EC), which can significantly decrease... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Symbiotic Scheduling for Shared Caches in Multi-core Systems Using Memory Footprint Signature

    Publication Year: 2011, Page(s):11 - 20
    Cited by:  Papers (6)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (421 KB) | HTML iconHTML

    As the trend of more cores sharing common resources on a single die and more systems crammed into enterprise computing space continue, optimizing the economies of scale for a given compute capacity is becoming more critical. One major challenge in performance scalability is the growing L2 cache contention caused by multiple contexts running on a multi-core processor either natively or under a virt... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Distributed Switch Architecture for On-Chip Networks

    Publication Year: 2011, Page(s):21 - 30
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (402 KB) | HTML iconHTML

    It is well-known that current Chip Multiprocessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity for such CMP and MPSoC designs at reasonable costs. However, as technology advances, links become the critical component in the NoC. First, because the power consumption of the link is ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation of Techniques to Improve Cache Access Uniformities

    Publication Year: 2011, Page(s):31 - 40
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (745 KB) | HTML iconHTML

    While higher associativities are common at L-2 or Last-Level cache hierarchies, direct-mapped and low associative caches are still used at L-1 level. Lower associativities result in higher miss rates, but have fast access times on hits. Another issue that inhibits cache performance is the non-uniformity of accesses exhibited by most applications: some sets are underutilized while others receive th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations

    Publication Year: 2011, Page(s):41 - 50
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (755 KB) | HTML iconHTML

    Within-die process variation causes cores, memories, and network resources in NoC-based CMPs to present different speeds and leakage power. In this context, thread mapping strategies that consider the effects of process variability on chip resources arise as a suitable choice to maximize performance while energy consumption constraints are satisfied. However, other factors, as the location of memo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation

    Publication Year: 2011, Page(s):51 - 62
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (375 KB) | HTML iconHTML

    As the number of cores in a chip increases, power consumption is becoming a major constraint in the design of chip multiprocessors. At the same time, server consolidation is gaining importance to take advantage of such a number of cores. Our goal is to alleviate this constraint by reducing the power consumption of chip multiprocessors used for consolidated workloads by means of the cache coherence... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • PEPCP: A Power-Efficient Parallel Coherence Protocol for Large-Scale Network-on-Chip

    Publication Year: 2011, Page(s):63 - 72
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    This paper presents a power-efficient parallel cache coherence protocol for network-on-chip interconnection fabric on many core chips. With the increasing numbers of processor cores, a directory-based cache coherence protocol is more scalable and expected to be used for the future chip architectures. However, the characterization of directory-based protocol on a NoC platform shows that many cycles... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory

    Publication Year: 2011, Page(s):73 - 82
    Cited by:  Papers (2)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (573 KB) | HTML iconHTML

    Hardware transactional memory (HTM) systems have been studied extensively along the dimensions of speculative versioning and contention management policies. The relative performance of several designs policies has been discussed at length in prior work within the framework of scalable chip-multiprocessing systems. Yet, the impact of simple structural optimizations like write-buffering has not been... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity

    Publication Year: 2011, Page(s):83 - 92
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (1182 KB) | HTML iconHTML

    An execute-ahead processor pre-executes instructions when a load miss would stall the processor. The typical design has several components that grow with the distance to execute ahead and need to be carefully balanced for optimal performance. This paper presents a novel approach which unifies those components and therefore is easy to implement and has no trouble to balance resource investment. Whe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Patrolling Mechanisms for Disconnected Targets in Wireless Mobile Data Mules Networks

    Publication Year: 2011, Page(s):93 - 98
    Cited by:  Papers (3)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (305 KB) | HTML iconHTML

    This paper considers the target patrolling problem which asks a set of mobile data mules to efficiently patrol a set of given targets. Since the time interval (also referred to visiting interval) for consecutively visiting to each target reflects the monitoring quality of this target, the goal of this research is to minimize the maximal visiting interval. This paper firstly proposes a basic algori... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Innovative Scheme for Increasing Connectivity in ZigBee Networks

    Publication Year: 2011, Page(s):99 - 104
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (970 KB) | HTML iconHTML

    ZigBee networks based on the IEEE 802.15.4 standard are designed for wireless sensor and control networks with low cost, low power consumption, and low data rate. To join in a ZigBee network with the tree topology, the hardware requirement of a device is simple and low threshold. However, a device may become an isolated node due to constraints of configuration parameters in the ZigBee network. To ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Distributed Flow-Based Guiding Protocol in Wireless Sensor Networks

    Publication Year: 2011, Page(s):105 - 114
    Cited by:  Papers (12)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (431 KB) | HTML iconHTML

    Guiding navigation is an important application in wireless sensor networks to make moving objects leave dangerous areas safely and quickly. However, guiding policy without considering congestion problem will postpone the escape time. In this paper, we propose a distributed flow-based guiding protocol for indoor environments to evacuate mobile objects from dangerous area to exit. Our goal is to con... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Bandwidth Allocation with QoS Guarantee for IEEE 802.16 Systems

    Publication Year: 2011, Page(s):115 - 119
    Cited by:  Papers (1)
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (294 KB) | HTML iconHTML

    Multimedia applications in wireless communication have shown notable increases over recent years. Specifically, Quality of Service (QoS) has become an important support mechanism in the context of a variety of applications which utilize network resources. The IEEE 802.16 standard for Wireless Metropolitan Area Networks (Wireless MAN) provides a complete QoS control structure designed to enable flo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Gradient-Based Aggregation in Forest of Sensors (GrAFS)

    Publication Year: 2011, Page(s):120 - 129
    Request permission for reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    In several sensing applications the parameter being sensed exhibits a high spatial correlation. For example, if the temperature of a region is being monitored, there are distinct hot and cold spots. The area close to the hot spots is usually warmer than average, with a temperature gradient between the hot and cold spots. We exploit this correlation of sensor data to form a forest of logical trees,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.