2011 VII Southern Conference on Programmable Logic (SPL)

The ISDB-T standard for digital broadcasting incorporates an extensive signal processing scheme in order to achieve reliable data integrity at the remote receiver. Particularly, the time interleaving stage requires a significant memory depth. Common implementations are often based in single-address access memories, which simplifies the algorithm logic but does not provide a cost-effective solution... View full abstract»

Low-Density Parity-Check (LDPC) codes are very efficient error control codes that are being considered as part of many next generation communication systems. In this paper FPGA implementations of two low complexity decoders are presented. These two implementations operate over any kind of parity check matrix, (including those randomly generated, structurally generated, either systematic or non sys... View full abstract»

N-Continuous OFDM systems have been proposed to achieve an important reduction of the out-of-band emitted power compared to conventional OFDM. However, system complexity has been increased and some resource demanding operations are necessary. So, this work considers the implementation in FPGA of the transmitter and also provides a novel analysis on the influence of the IFFT length in the represent... View full abstract»

In this work we present the design of an FPGA based platform for acquiring and storing signals for SDR applications. The system comprises an embedded RISC processor, an A/D converter, RAM memory chips and a DMA controller core. This last component was designed from scratch to meet the high data rate and bulk requirements. The software needed to control the system was also developed and a Graphical... View full abstract»

Optical Transport Networks (OTN) have emerged as a key enabler to increase the capacity of current telecommunication infrastructure. ITU-T Recommendation G.709 describes these networks by defining a flexible frame structure capable of carrying different client data signals. Recently, G.709 framer devices have received much attention from the telecommunication industry as next generation 10/40/100G... View full abstract»

This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the para... View full abstract»

As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requireme... View full abstract»

This paper describes a security-aware cache targeting field programmable gate array (FPGA) technology. Our design is based on an architecture with a remapping table, which provides resilience against side-channel timing attacks. We show how this cache design can be optimised for FPGA re sources by an index decoder with content addressable memory structure, which can be customized to meet various r... View full abstract»

This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitiga... View full abstract»

The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Pa... View full abstract»

Currently the market and the academic community have required applications of image and video processing with several real-time constraints. In order to seek an alternative design that allows the rapid development of real time image processing systems this paper proposes an unified hardware architecture for some image filtering algorithms in space domain, such as windowing-based operations, which ... View full abstract»

This paper deals with the problem of the design of an all-digital implementation of a three-phase PLL and the control logic of a shunt active filter implemented with a Multilevel Current Source Inverter (MCSI). The active filter is connected to the medium voltage level of a power distribution system where compensation of reactive power and harmonics is mandatory. The PLL is essential to obtain a r... View full abstract»

In this paper we present the design, implementation and experimental validation of a FPGA based position servo controller for a DC motor with dry friction. VHDL and block diagram modules for trajectory generation, encoder signal decoding, PI controller and PWM control signal generation are described. The control system is implemented in the DE3 board of Terasic Technologies Inc using Quartus II en... View full abstract»

In this paper, we examine the problem of abstracting the design process for heterogeneous CPU/FPGA systems from the perspective of a group of engineers designing telecommunications systems, and propose a design flow that addresses the constraints imposed in an industrial context whilst striving for maximal compatibility with existing tools and research projects. We thus present a modular and exten... View full abstract»

This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multi... View full abstract»

In this paper, we present a heuristic algorithm for bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks (CLBs), Block RAMs and Multipliers (MULs). The desired min-cut bipartition has to satisfy m constraints arising from given balance ratios, one for each type of resource. The netlist is represented as a hypergraph, whose... View full abstract»

In impulse-based UWB systems, positional accuracy is inversely proportional to the signal bandwidth. In this work, a number of anchor nodes are located at fixed positions in an indoor environment transmitting synchronized 2.5ns pulses with Differential Binary Phase Shift Keying (DBPSK) modulation. An UWB receiver mounted on a mobile robot utilizes Time Difference of Arrival (TDOA) between pairs of... View full abstract»

In this work an FPGA-based emulator of a pulse-mode neutron detector system is presented. The equipment emulates the digital output of a discriminator circuit and permits the generation of pulse trains ranging from 0.5 pulse/s to 1 Mpulse/s. The emulation is based on a synchronous version of a Poisson process generator using Bernoulli trials. The emulator is controlled via a serial connection to a... View full abstract»

This paper presents experiences in applying modern functional verification to a configurable decimal floating point Adder / Subtractor core targeted to programmable logic. Despite its huge input space, a number of hard-to-verify corner cases are identified. Two different verification frameworks were applied in order to develop testbenches: OVM and Truss. These tesbenches were built to be independe... View full abstract»