Proceedings Design, Automation and Test in Europe

23-26 Feb. 1998

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  • Proceedings Design, Automation and Test in Europe

    Publication Year: 1998
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    Freely Available from IEEE
  • Functional scan chain testing

    Publication Year: 1998, Page(s):278 - 283
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (74 KB)

    Functional scan chains are scan chains that have scan paths through a circuit's functional logic and flip-flops. Establishing functional scan paths by test point insertion (TPI) has been shown to be an effective technique to reduce the scan overhead. However, once the scan chain is allowed to go through functional logic, the traditional alternating test sequence is no longer enough to ensure the c... View full abstract»

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  • Reconfigurable logic for systems on a chip

    Publication Year: 1998
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7 KB)

    Summary form only given. The electronic systems of the future will be implemented in terms of multi-million gate "systems on a chip". These systems will require an enormous investment in design and manufacturing; yet the pace of technological change (e.g., new algorithm development, new processor and memory designs) and ever changing requirements puts them in danger of obsolescence soon after they... View full abstract»

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  • Estimation of the defective I/sub DDQ/ caused by shorts in deep-submicron CMOS ICs

    Publication Year: 1998, Page(s):490 - 494
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB)

    The defective I/sub DDQ/ in deep-submicron full complementary MOS circuits with shorts is estimated. High performance and also low power scenarios are considered. The technology scaling, including geometry reductions of the transistor dimensions, power supply voltage reduction, carrier mobility degradation and velocity saturation, is modeled. By means of the characterization of the saturation curr... View full abstract»

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  • Silicon debug of systems-on-chips [session introduction]

    Publication Year: 1998, Page(s):632 - 633
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (14 KB)

    Summary form only given. Modern society's dependence on information and communication infrastructure (ICI) is so deeply entrenched that it should be treated on par with other critical lifelines of our existence, such as water and electricity. As is the case with any true lifeline, ICI must be reliable, affordable, and sustainable. Meeting these requirements (especially sustainability) is a continu... View full abstract»

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  • Address bus encoding techniques for system-level power optimization

    Publication Year: 1998, Page(s):861 - 866
    Cited by:  Papers (60)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (174 KB)

    The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, th... View full abstract»

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  • Author index

    Publication Year: 1998, Page(s):989 - 993
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    Freely Available from IEEE
  • XFVHDL: a tool for the synthesis of fuzzy logic controllers

    Publication Year: 1998, Page(s):102 - 107
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    A tool for the synthesis of fuzzy controllers is presented in this paper. This tool takes as input the behavioral specification of a controller and generates its VHDL description according to a target architecture. The VHDL code can be synthesized by means of two implementation methodologies, ASIC and FPGA. The main advantages of using this approach are rapid prototyping, and the use of well-known... View full abstract»

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  • ATM traffic shaper: ATS

    Publication Year: 1998, Page(s):96 - 101
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The design and Implementation of an ATM Traffic Shaper (ATS) is described. This IC was realised on a 0.35 μm CMOS technology. The main function of the ATS is the collection of low bit rate traffic to fill a higher bit rate pipe in order to reduce the cost of ATM based services, nowadays mainly influenced by transmission cost. The circuit fits in several ATM system configurations but mainly will... View full abstract»

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  • Hardware resource allocation for hardware/software partitioning in the LYCOS system

    Publication Year: 1998, Page(s):22 - 27
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software part... View full abstract»

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  • Novel technique for testing FPGAs

    Publication Year: 1998, Page(s):89 - 94
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    This paper presents a novel technique for testing Field Programmable Gate Arrays (FPGAs), suitable for use in the case of frequent FPGA reuse and rapid dynamic modifiability of the implemented function View full abstract»

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  • On the reuse of symbolic simulation results for incremental equivalence verification of switch-level circuits

    Publication Year: 1998, Page(s):624 - 629
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    Incremental methods are successfully applied to deal with successive verifications of slightly modified switch-level networks. That is, only those parts affected by the changes are symbolically traversed for verification. In this paper, we present an incremental technique for symbolic simulators which is inspired in both existing incremental techniques for non-symbolic simulators and a token-passi... View full abstract»

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  • PASTEL: a parameterized memory characterization system

    Publication Year: 1998, Page(s):15 - 20
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    PASTEL is a parameterized memory characterization system which extracts the characteristics of ASIC on-chip-memories such as delay, timing and power consumption which are important in LSI logic design. PASTEL is a fully-automated process from exact wire-RC extraction through circuit reduction, input vector generation, waveform measurement, data-sheet and library creation. The circuit reduction sch... View full abstract»

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  • Design-manufacturing interface. I. Vision [VLSI]

    Publication Year: 1998, Page(s):550 - 556
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is partitioned into a number of specific tasks. Oft... View full abstract»

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  • Design of future systems

    Publication Year: 1998, Page(s):343 - 347
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    This paper describes a vision in which future systems consisting of novel hardware and software components are designed and implemented by a single type of professional engineer. That professional has more in common with today's programmer than a hardware designer, although both of these existing bodies of professionals have a strong contribution to make to understanding, defining and bringing abo... View full abstract»

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  • RAM-based FPGAs: a test approach for the configurable logic

    Publication Year: 1998, Page(s):82 - 88
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic test configurations to fully test the whole matrix of CLBs. In the proposed test configurations, all the CLBs have exactly the same confi... View full abstract»

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  • An effective general connectivity concept for clustering

    Publication Year: 1998, Page(s):398 - 405
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    This paper shows how algorithmic techniques and parallel processing can speed up general connectivity computation. A new algorithm, called Concurrent Group Search Algorithm (CGSA), is proposed that divides N(N-1)/2 vertex pairs into N-1 groups. Within each group general connectivities of all pairs can be calculated concurrently. Our experimental results show that this technique can achieve speedup... View full abstract»

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  • Graphical entry of FSMDs revisited: putting graphical models on a solid base

    Publication Year: 1998, Page(s):931 - 932
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24 KB)

    This paper discusses issues of graphical modelling of Finite State Machines with Datapath (FSMDs). Tools supporting the graphical entry of state based systems are usable by intuition, but need to be based on an exact definition of semantics of graphical elements. This paper proposes to define semantics of graphical models based on the hardware description language VHDL View full abstract»

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  • Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration

    Publication Year: 1998, Page(s):583 - 587
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences only as necessary to restore the fault coverage of the original sequence. Techniques to speed-up the restoration ... View full abstract»

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  • Sequential equivalence checking without state space traversal

    Publication Year: 1998, Page(s):618 - 623
    Cited by:  Papers (41)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    Because general algorithms for sequential equivalence checking require a state space traversal of the product machine, they are computationally expensive. In this paper we present a new method for sequential equivalence checking which utilizes functionally equivalent signals to prove the equivalence of both circuits, thereby avoiding the state space traversal. The effectiveness of the proposed met... View full abstract»

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  • Design of fault-secure parity-prediction Booth multipliers

    Publication Year: 1998, Page(s):7 - 14
    Cited by:  Papers (3)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The basic drawback of parity prediction arithmetic operators is that they may not be fault secure for single faults. In a recent work we have proposed a theory for achieving fault secure design for parity prediction multipliers and dividers. This paper has not considered the case of Booth multipliers using operand recoding. This case is analyzed here. Parity prediction logic and fault secure imple... View full abstract»

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  • A cell and macrocell compiler for GaAs VLSI full-custom design

    Publication Year: 1998, Page(s):947 - 948
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    A gallium arsenide automated layout generation system (OLYMPO) for SSI, MSI and LSI circuits used in GaAs VLSI design has been developed. We introduce a full-custom layout style, called RN-based cell model, that it is suited to generate low self-inductance circuit layouts of cells and macrocells. The cell compiler can be used as a cell library builder and it is embedded in a random logic macrocell... View full abstract»

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  • Synthesis of communicating controllers for concurrent hardware/software systems

    Publication Year: 1998, Page(s):912 - 913
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Two main aspects in hardware/software co-design are hardware/software partitioning and co-synthesis. Most co-design approaches work only on one of these problems. In this paper, an approach coupling hardware/software partitioning and co-synthesis is presented, working fully-automatically. The techniques have been integrated in the co-design tool COOL supporting the complete design flow from system... View full abstract»

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  • Parallel VHDL simulation

    Publication Year: 1998, Page(s):159 - 163
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    In this paper we evaluate parallel VHDL simulation based on conservative parallel discrete event simulation (conservative PDES) algorithms. We focus on a conservative simulation algorithm based on critical and external distances. This algorithm exploits the interconnection structure within the simulation model to increase parallelism. Further, a general method is introduced to automatically transf... View full abstract»

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  • Restructuring logic representations with easily detectable simple disjunctive decompositions

    Publication Year: 1998, Page(s):755 - 759
    Cited by:  Papers (6)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    Simple disjunctive decomposition is a special case of logic function decomposition, where variables are divided into two disjoint sets and there is only one newly introduced variable. This paper presents that many simple disjunctive decompositions can be found easily by detecting symmetric variables or checking variable cofactors. We also propose an algorithm that constructs a new logic representa... View full abstract»

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