Parallel Architectures, Algorithms, and Networks, 1997. (I-SPAN '97) Proceedings., Third International Symposium on

20-20 Dec. 1997

Filter Results

Displaying Results 1 - 25 of 82
  • Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN'97)

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (445 KB)
    Freely Available from IEEE
  • Index of authors

    Publication Year: 1997, Page(s):501 - 503
    Request permission for commercial reuse | PDF file iconPDF (91 KB)
    Freely Available from IEEE
  • BaLinda: a simple parallel programming model with active objects

    Publication Year: 1997, Page(s):23 - 29
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    This paper presents the BaLinda model, based on last in/first out threads that interact via a shared tuplespace, and discusses the idea of using function based objects as the basic unit of parallel execution, and the hierarchical structure to partition tuplespaces. It is argued that the two-level parallel execution, both within and between objects, are well suited to scalable parallel platforms wi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An NC parallel algorithm for generalized vertex-rankings of partial k-trees

    Publication Year: 1997, Page(s):105 - 111
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    A c-vertex-ranking of a graph G for a positive integer c is a labeling of the vertices of G with integers such that, for any label i, deletion of all vertices with labels >i leaves connected components, each having at most c vertices with label i. We present a parallel algorithm to find a c-vertex-ranking of a partial k-tree using the minimum number of ranks. This is the first parallel algorith... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A polynomial time algorithm for reconfiguring the 1 1/2 track-switch model with PE and bus faults

    Publication Year: 1997, Page(s):16 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. Various strategies to restructure the faulty physical system into the ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cover model: a framework for design and execution of distributed applications

    Publication Year: 1997, Page(s):98 - 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    Many problems of distributed object-oriented applications can be uniformly resolved in the frame of approach based on the concept of cover. The cover is defined as an environment that transparently controls all aspects of object's community, life: creation, interaction etc. To enable transparency, an object-oriented application must obey a principle of late binding, a reference to server object be... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reliable broadcasting and secure distributing in channel networks

    Publication Year: 1997, Page(s):472 - 478
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    Let T1, ···, Tn be n spanning trees rooted at node r of graph G. If for any node ν of G, among the n paths from r to ν, each path in each spanning tree of T 1, ···, Tn, there are k (k⩽n) internally disjoint paths, then T1, ···, Tn, are said to be (k, n)-indepen... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Critical sections and producer/consumer queues in weak memory systems

    Publication Year: 1997, Page(s):56 - 63
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    In machines with a weak memory consistency model, the ordering constraints on memory accesses are few. In order to properly program these machines, certain powerful explicit synchronization instructions are additionally provided by their architecture. We show that although a solution to the critical section problem (also referred to as the mutual exclusion problem) is impossible without such power... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A method for estimating optimal unrolling times for nested loops

    Publication Year: 1997, Page(s):376 - 382
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    Loop unrolling is one of the most promising parallelization techniques, because the nature of programs causes most of the processing time to be spent in their loops. Unrolling not only the innermost loop but also outer loops greatly expands the scope for reusing data and parallelizing instructions. Nested-loop unrolling is therefore a very effective way of obtaining a higher degree of parallelism.... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CASS: an efficient task management system for distributed memory architectures

    Publication Year: 1997, Page(s):289 - 295
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the application characteristics. On the other hand, the task of limiting the parallelism in a chosen parallel algorithm is best handled by the compiler or operating system for the target MPP machine. Toward this end, we have develop... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the shuffle-exchange permutation network

    Publication Year: 1997, Page(s):165 - 171
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The shuffle-exchange permutation network (SEPn) is a fixed degree Cayley graph which has been proposed as a basis for massively parallel systems. We propose a routing algorithm with an upper bound of (5/8)n2+O(n), where n is the length of the permutation. (This improves on a (9/8)n2 routing algorithm described earlier (Latifi and Srimani, 1996)). Thus, the diameter... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A parallel pipelined renderer for time-varying volume data

    Publication Year: 1997, Page(s):9 - 15
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    This paper presents a strategy for efficiently rendering time-varying volume data on a distributed-memory parallel computer. Visualizing time-varying volume data take both large storage space and long computation time. Instead of employing all processors to render one volume at a time, a pipelined rendering approach partitions processors into groups so that multiple volumes can be rendered concurr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient tree-based multicast in wormhole-routed 2D meshes

    Publication Year: 1997, Page(s):494 - 500
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    This paper proposes a tree-based routing scheme for multicasting general messages of arbitrary length on 2D mesh networks. The scheme takes into account of the characteristics of the programming interface and constructs a quad-branch multicast (QBM) tree for transmitting the given multicast. To maintain the QBM tree, we will describe how routers can be designed and initialized, and how the multica... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An implementable dynamic automatic self-stabilizing protocol

    Publication Year: 1997, Page(s):91 - 97
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    The notion of self-stabilization was first introduced by Dijkstra: it is the property for a system to eventually recover by itself a legitimate state after any perturbation modifying the memory state. This paper proposes a dynamic automatic self-stabilizing protocol. This algorithm runs in the fully asynchronous message-passing model in which messages can also be corrupted. The principle of the al... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient class of SEC-DED-AUED codes

    Publication Year: 1997, Page(s):410 - 416
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    In this paper, an efficient method for constructing a class of Single Error Correcting and Double Error Detecting and All Unidirectional Error Detecting (SEC-DED-AUED) codes has been presented. The encoding/decoding algorithms proposed with this method can be implemented with a simple and faster hardware. Also, in ROM based implementation, it results in significant saving of word-length. This sche... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A tampering protocol for reducing the coherence transactions in regular computation

    Publication Year: 1997, Page(s):465 - 471
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    This paper proposes a tampering protocol for reducing the coherence transactions in the computations with regular communication patterns. This protocol is a subsidiary of the conventional cache-coherence protocol and is activated on a memory-block basis. If activated for a block, the exclusive copy of that block is frozen in the cache and is accessed (i.e., tampered) with no coherence transactions... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A pipelined TDM optical bus with improved performance

    Publication Year: 1997, Page(s):49 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    We propose a pipelined asynchronous time division multiplexing optical bus. Such a bus can use one of the two hardware priority schemes, the linear priority scheme and the round-robin priority scheme. Our simulation results show that the performance of the proposed bus is significantly better than the performances of known pipelined synchronous time division multiplexing optical buses View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An evolutionary approach for scheduling in parallel processor systems

    Publication Year: 1997, Page(s):369 - 375
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    Task scheduling is essential for the proper functioning of parallel processor systems. Scheduling of tasks onto networks of parallel processors is an interesting problem that is well-defined and documented in the literature. However, most of the available techniques are based on heuristics that solve certain instances of the scheduling problem very efficiently and in reasonable amounts of time. Th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Speech support in wireless, multihop networks

    Publication Year: 1997, Page(s):282 - 288
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    In this paper we address the evaluation of speech quality through a wireless network as perceived by the user. User perceived evaluation (in addition to the usual network metrics including delay, throughput, packet loss statistics etc.) is critical in the design of wireless multimedia networks where speech and video play a key role and are affected by several factors, such as network performance a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hardware synchronization of massively parallel processes in distributed systems

    Publication Year: 1997, Page(s):157 - 164
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    In this paper a new method is proposed to synchronize massively parallel processes in distributed multiprocessor systems. The method is an extension of that used in arbitration systems like Futurebus+. It also uses three global synchronization lines and a distributed synchronizer, and can be applied without changes to the existing hardware. The method allows to carry out two alternative synchroniz... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new general purpose parallel database system

    Publication Year: 1997, Page(s):2 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    This paper is concerned with the transparent parallelisation of declarative database queries, based on theoretical principles. We have designed an entire database architecture suitable for use on any general-purpose parallel machine. This architecture addresses the shortcomings in flexibility and scalability of commercial parallel databases. A substantial benefit is that the mathematical principle... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Approximation Algorithms

    Publication Year: 1997, Page(s): 232
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A decentralised scheme for multi-node broadcasting on hypercubes

    Publication Year: 1997, Page(s):487 - 493
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    In this paper, we study the following multi-node broadcast problem on hypercubes, which is an asynchronous and repetitive version of all-to-all broadcast problem. Suppose that nodes of a hypercube asynchronously repeat broadcasting a piece of information called a token. They can asynchronously initiate their broadcasts while other broadcasts are in process. The multi-node broadcast problem, which ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The architecture of OCMP and its evaluation

    Publication Year: 1997, Page(s):71 - 77
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    By gathering multiple processors in one LSI chip, communication delay between processors becomes shorter and then efficient fine/medium grain parallel processing can be realized. The authors propose a new processor architecture called OCMP (On-Chip Multi-Processing Architecture). OCMP has two characteristics: one is the instruction level dispatching mechanism; and the other is the divided cache sy... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An operation placement and scheduling scheme for cache and communication localities in fine-grain parallel architectures

    Publication Year: 1997, Page(s):390 - 396
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    With increasing on-chip hardware, concurrency is a way to bridge the gap between the computational power demanded by the applications and that afforded by the computer platforms. Although parallel systems are increasingly popular they remain very difficult to program. In fact, most compilers require the programmer to specify how to partition data or map program code to the system's processors. To ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.