Proceedings International Test Conference 1997

1-6 Nov 1997

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Displaying Results 1 - 25 of 138
  • The application of novel failure analysis techniques for advanced multi-layered CMOS devices

    Publication Year: 1997, Page(s):304 - 309
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

    The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection.... View full abstract»

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  • Proceedings International Test Conference 1997

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (636 KB)
    Freely Available from IEEE
  • Scan encoded test pattern generation for BIST

    Publication Year: 1997, Page(s):548 - 556
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (914 KB)

    This paper presents an improved scan-based BIST scheme which achieves very high fault coverage without any modification of the mission logic, i.e. no test point insertion, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. The approach utilizes scan order and its polarity in scan synthesis, effectively converting it into a ROM encoding a few test ... View full abstract»

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  • Author index

    Publication Year: 1997, Page(s):1053 - 1054
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    Freely Available from IEEE
  • Low current and low voltages-the high-end op amp testing challenge

    Publication Year: 1997, Page(s):796 - 801
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    State-of-the-art op amps with input bias currents in the fA range and offset voltages of several μV present special test problems. The authors discuss the measurement problems and their possible solutions. The topics discussed include: DSP based input bias current measurement; leakage current compensation; and current loop feedback View full abstract»

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  • Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits

    Publication Year: 1997, Page(s):786 - 795
    Cited by:  Papers (68)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    This paper describes a new built-in self test (BIST) technique suitable for both functional and structural testing of analog and mixed-signal circuits based on the oscillation-test methodology. Analog-to-digital converter (ADC) is used as a test vehicle to demonstrate the capability of the proposed OBIST technique for both functional and structural testing. Design of different parts of OBIST struc... View full abstract»

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  • On-chip measurement of the jitter transfer function of charge-pump phase-locked loops

    Publication Year: 1997, Page(s):776 - 785
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB)

    An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two methods. Both rely on delta-sigma modulation to shape the unavoidable quantization noise to high frequencies. This noise is filtered by the lowpass characteristic of the device and has a minimal impact on the test results. For ... View full abstract»

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  • System level boundary scan in a highly integrated switch

    Publication Year: 1997, Page(s):636 - 639
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    JTAG and continuity testing can only go so far at a board or module testing level. When all of the pieces come together, employing boundary scan (IEEE 1149.1) techniques at a system level can significantly reduce the time it takes to test a large product with literally thousands of interconnections. Although there are many benefits to system level JTAG, there are pitfalls as well. This paper descr... View full abstract»

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  • Experimental results for current-based analog scan

    Publication Year: 1997, Page(s):768 - 775
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    This paper presents the design of current-mode circuits for analog scan, which include the highly accurate current-mirror scan latches and the analog shift registers. Experimental data from a test chip fabricated in Orbit 2-micron CMOS Foresight process illustrates that the accuracy of the circuits is sufficient for use in analog on-chip scan-based testing. The interface between analog scan and th... View full abstract»

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  • Optical communication channel test using BIST approaches

    Publication Year: 1997, Page(s):626 - 635
    Cited by:  Papers (3)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    Novel Built-In Self-Test (BIST) approaches for integrated optoelectronic systems are presented The methods are compatible with scan chain design and allow testing the internal functionality of the device, the interconnection between modules, the analog characteristics of the transmitters and receivers and the Bit Error Rate (BER) of the channels. The proposed approaches enable system evaluation un... View full abstract»

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  • HABIST: histogram-based analog built in self test

    Publication Year: 1997, Page(s):760 - 767
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    This histogram based method of test collects a statistical representation of the activity at a node and processes that representation using a template histogram as a reference. In most cases, no special stimulus is required-data is collected in-situ, while the circuit under test is functioning. (Alternatively, analog stimulus, e.g. using a pseudo random sequence generator or stored digital vectors... View full abstract»

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  • Pentium(R) Pro processor design for test and debug

    Publication Year: 1997, Page(s):294 - 303
    Cited by:  Papers (48)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB)

    This paper describes the Design for Test (DFT) and silicon debug features of the Pentium(R) Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led the design team to a custom low-area DFT approach, coupled with a manually-written test methodology which targeted seve... View full abstract»

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  • P1149.4-problem or solution for mixed-signal IC design?

    Publication Year: 1997
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    The issue of whether the proposed P1149.4 Standard for a Mixed-Signal Test Bus will be a net benefit to board level design and test seems to be more or less settled: for the extremely dense circuit boards which will be commonplace in five years, and in today's multi-chip modules, P1149.4 offers a solution where no other exists. P1149.4 was aimed at solving test issues for these mixed-signal boards... View full abstract»

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  • Testability analysis and ATPG on behavioral RT-level VHDL

    Publication Year: 1997, Page(s):753 - 759
    Cited by:  Papers (38)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on a... View full abstract»

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  • The fail-stop controller AE11

    Publication Year: 1997, Page(s):567 - 577
    Cited by:  Papers (11)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB)

    Using on-chip fault detection measures the fail-stop controller. AE11 was developed for safety critical applications aiming at high volume production of automotive and railway electronics. The trade-off between high defect coverage, short reaction time to faults and low chip area overhead results in a combination of concurrent checking, built-in self-test and built-in current-monitoring (IDDQ... View full abstract»

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  • Dynamic testing of ADCs using wavelet transforms

    Publication Year: 1997, Page(s):379 - 388
    Cited by:  Papers (9)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    This paper introduces a new method for evaluating non-idealities in ADCs using wavelet transforms. Compared with conventional testing methods, this method can shorten the test time and improve test quality during production testing of ADCs View full abstract»

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  • Design of cache test hardware on the HP PA8500

    Publication Year: 1997, Page(s):286 - 293
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    There are many difficulties inherent in the testing of large on-chip caches. This paper presents some of these problems and provides motivation for solving them. After the motive has been established, the techniques used to test the PA8500 on-chip caches are described. This is followed by a detailed explanation of the test hardware, and an example of how it is used View full abstract»

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  • Fault model extension for diagnosing custom cell fails

    Publication Year: 1997, Page(s):617 - 624
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    This paper describes an extension of the standard, stuck-at fault model typically used for diagnostics. By defining stuck-at faults at all levels of a design hierarchy, diagnostic simulation has been able to succinctly identify a number of custom circuit design and modeling errors. Approximately half of these errors were not well identified by conventional diagnostics View full abstract»

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  • A novel functional test generation method for processors using commercial ATPG

    Publication Year: 1997, Page(s):743 - 752
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper describes a novel method for hierarchical functional test generation for processors which targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Applying the te... View full abstract»

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  • On-line testable logic design for FPGA implementation

    Publication Year: 1997, Page(s):471 - 478
    Cited by:  Papers (19)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    In recent years, a number of logic design techniques for look-up table (LUT) based FPGAs have been proposed. However, none of these address issues such as fault detection or testability. This paper presents an algorithm which maps optimized Boolean expressions into look-up table based FPGAs. This mapping automatically incorporates testability features into designs, allowing on-line detection of fa... View full abstract»

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  • To DFT or not to DFT?

    Publication Year: 1997, Page(s):557 - 566
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (900 KB)

    Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first st... View full abstract»

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  • A DSP-based feedback loop for mixed-signal VLSI testing

    Publication Year: 1997, Page(s):670 - 674
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Implementing a feedback loop system for a mixed-signal VLSI test system by using an embedded digital signal processing (DSP) unit provides superior flexibility in device testing applications. This paper describes such a DSP feedback loop within the context of a mixed-signal VLSI test system, while discussing a number of potential applications and their implications View full abstract»

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  • IEEE P1149.4-almost a standard

    Publication Year: 1997, Page(s):174 - 182
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    The IEEE P1149.4 Mixed-Signal Test Bus Working Group is on the cusp of delivering a document that will finally standardize the architecture for, and the method of access to, the analog portion of mixed-signal circuits for test and diagnostic applications. This Standard will have the same profound effect on the design and test community that IEEE 1149.1 had previously. P1149.4 gives the test infras... View full abstract»

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  • A low-cost massively-parallel interconnect test method for MCM substrates

    Publication Year: 1997, Page(s):370 - 378
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    This paper introduces a new approach for interconnect testing of unpopulated MCM substrates. Defect detection and diagnosis is performed using a variation of methods that have traditionally been applied using Boundary Scan registers. The new approach involves parallel application of digital signatures to all nets, while capturing the responses at every node. The responses of fault-free nets are id... View full abstract»

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  • Manufacturing pattern development for the Alpha 21164 microprocessor

    Publication Year: 1997, Page(s):278 - 285
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    Functional test patterns play a key role in the test strategy of many microprocessors. This paper describes the process of creating and fault grading an initial set of functional test vectors. The fault simulation results are used to identify design verification test (DVT) hard faults and to guide additional test development. Moreover, this paper details the effectiveness of test creation heuristi... View full abstract»

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