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1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon

8-10 Oct. 1997

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Displaying Results 1 - 25 of 43
  • 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (372 KB)
    Freely Available from IEEE
  • The power of dynamic reconfiguration

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (42 KB)

    Summary form only given. Advances in semiconductor technology have led to many devices in which the computing devices can be configured as the computation proceeds. Field Programmable Gate Arrays is a typical commercially available configurable device. Such configurability offers several opportunities to speed-up computations. However, algorithmic innovations are needed to exploit such features to... View full abstract»

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  • Test strategy sensitivity to floating gate fault parameter

    Publication Year: 1997, Page(s):186 - 195
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (563 KB)

    This paper studies the detectability of floating gate faults considering static voltage, dynamic voltage and static current strategies. It is shown that the behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters (polysilicon-to-bulk capacitance). It is shown that a floating gate fault can induce abnormal logic values, additional delays or increase... View full abstract»

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  • Optical interconnects for commodity silicon technologies

    Publication Year: 1997, Page(s):201 - 202
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (130 KB)

    Summary form only given. The concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit now appears to be a reality. The development of such optoelectronic-VLSI technology and its compatibility with submicron CMOS technology, is discussed by the author. View full abstract»

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  • RF MEMS for digitally-controlled front-end components

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (61 KB)

    Summary form only given, as follows. In recent years the field of microelectromechanical systems (MEMS) has grown very fast and merged with many defense and commercial applications. Much of this activity has been driven by the ability of MEMS to miniaturize, reduce the cost, and improve the performance of transducers and actuators previously fabricated by hybrid techniques. These benefits have ste... View full abstract»

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  • Economics modeling of multichip systems testing strategies

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (54 KB)

    Summary form only given, as follows. To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply Design For Test (DFT) and Built-in Self Test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to det... View full abstract»

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  • 1996 Innovative Systems In Silicon Conference - Index

    Publication Year: 1997, Page(s): 372
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    Freely Available from IEEE
  • Fault tolerance of one-time programmable FPGAs with faulty routing resources

    Publication Year: 1997, Page(s):155 - 164
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper presents a novel approach for fault tolerance of one-time programmable FPGAs by reassignment of routing resouces. As the underlying problem is NP-complete, a greedy algorithm is proposed to provide rapid, but suboptimal solutions. Due to the one-time programmable characteristic of the switches (commonly referred to as antifuses), only unused (fault-free) routing resources must be utiliz... View full abstract»

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  • Electrical modeling and simulation for mixed-signal interconnect and packaging

    Publication Year: 1997, Page(s):82 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    The explosive growth of wireless communications, combined with the rapid advances in high-performance portable computing, are driving the microelectronics industry toward the development of a variety of multi-functional, low-cost, compact, mixed-signal electronic products. These new products call for novel, often revolutionary, practices in functional block integration and packaging. Some of the c... View full abstract»

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  • Smartcards: portable security

    Publication Year: 1997, Page(s):259 - 265
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Smartcards are one of the fastest growing market segments in the field of microelectronics, since they offer an easy way to implement secure transactions. In this paper we will consider the main characteristics of smartcards, with special regard to the ones used for secure transactions, and discuss the main market and technology trends View full abstract»

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  • A scalar cost function for analyzing the quality of totally self-checking design methodologies

    Publication Year: 1997, Page(s):196 - 200, 200a, 200b
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    This paper proposes a scalar cost function for analyzing the quality of Totally Self-Checking combinational devices; in particular the presented evaluator allows one to take into account other significant aspects affecting a TSC implementation rather than area overhead. The cost function is based on a measure which dynamically defines the probability to achieve the TSC goal at cycle t with respect... View full abstract»

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  • Efficient controller design for telescopic units

    Publication Year: 1997, Page(s):290 - 299
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    Telescopic units represent an effective and innovative design option for increasing the average throughput of a combinational block. Throughput improvement is obtained at the price of a small reduction in average latency by allowing the unit to run with variable latency. Although this design paradigm has proved to be very effective, there are still some issues that need to be addressed before it c... View full abstract»

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  • A reconfigurable Markov chain simulator for analysis of parallel systems

    Publication Year: 1997, Page(s):107 - 116
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Markov chain is a convenient tool to analyze parallel systems for architects who are not experts of theoretical analysis. However, it is sometimes difficult to use especially when the model becomes complicated or extremely small probabilities are used in the model. In this paper, we propose a reconfigurable Markov chain simulation system and evaluate on a reconfigurable testbed. In this system, a ... View full abstract»

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  • High speed lensless integrated proximity sensor

    Publication Year: 1997, Page(s):126 - 135
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    An integrated sensor array has been developed using lensless techniques that produces a high accuracy proximity measurement from contact to 18 mm. An integrated optical detector and processing circuitry chip was developed for this application. It locates the brightest spot within an optical array which will output the proximity position every 5.3 μs View full abstract»

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  • The microprocessor is no longer general purpose: why future reconfigurable platforms will win

    Publication Year: 1997, Page(s):2 - 12
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    The paper is a proposal for a radical methodological change in R&D of dynamically reconfigurable circuits. The paper illustrates, that the current main stream approach based on placement and routing is not very likely to obtain the area-efficiency and throughput needed to cope with the emerging crisis cost of future silicon technology generations. The proposed changes include both: architectur... View full abstract»

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  • Design and characterization of next-generation micromirrors fabricated in a four-level, planarized surface-micromachined polycrystalline silicon process

    Publication Year: 1997, Page(s):144 - 154
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1312 KB)

    This paper describes the design and characterization of several types of micromirror devices to include process capabilities, device modeling, and test data resulting in deflection versus applied potential curves. These micromirror devices are the first to be fabricated in the state-of-the-art four-level planarized polysilicon process available at Sandia National Laboratories known as the Sandia U... View full abstract»

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  • A 16 GHz fast RISC engine using GaAs/AlGaAs and SiGe HBT technology

    Publication Year: 1997, Page(s):72 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    Wafer Scale Hybrid Packages (WSHPs) or MultiChip Modules (MCMs) have provided a breakthrough in system packaging for high clock rate systems. Based on this technology a 2 GHz Fast RISC demonstration integer-only computational engine has been designed, and is submitted for fabrication. This design involved use of Heterojunction Bipolar Transistors (HBTs) in the GaAs/AlGaAs materials system. This pa... View full abstract»

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  • The challenges in achieving sub-100 nm MOSFETs

    Publication Year: 1997, Page(s):52 - 60
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    The continued scaling of the MOS transistor to smaller feature sizes has been the prime factor in the remarkable advancements in integrated circuits over the past 25-30 years. This is due to the fact that successively smaller devices have allowed continued rapid improvements in the level of integration and performance. While sub-100 nm MOSFETs have been built in the laboratory, it is by no means s... View full abstract»

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  • Architecture, defect tolerance, and buffer design for a new ATM switch

    Publication Year: 1997, Page(s):248 - 258
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    This paper presents a modular architecture for a scalable ATM-switch. The cell routing function, and the associated queueing, is distributed over many small clusters of nodes, called basic modules. These basic modules are hierarchically interconnected to form larger switches. In a basic module, every node is interconnected with adjacent nodes in the same module with three of its four links. The fo... View full abstract»

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  • A dual mode IEEE multiplier

    Publication Year: 1997, Page(s):282 - 289
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We present an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the latency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fifteen logic levels. A single-precision multiplication can be followed immediately by another multi... View full abstract»

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  • System-level power evaluation metrics

    Publication Year: 1997, Page(s):323 - 330
    Cited by:  Patents (65)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    High-level power estimation is a key issue for IC designers and system engineers. The goal is to widely explore the architectural design space and to compare alternative solutions, while maintaining an acceptable accuracy and a competitive design time. In this paper, an approach is proposed for evaluating the system-level power consumption of embedded systems implemented by using VLSI circuits. Ac... View full abstract»

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  • How to lay out arrays spared by rows and columns

    Publication Year: 1997, Page(s):30 - 40
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    Perhaps the most common fault tolerant architecture configures a nominal t×at array using bt dedicated spare rows and ct dedicated spare columns. We counterexample an outstanding conjecture by constructively showing how dedicated sparing can be laid out in area proportional to the number of elements. However, we find that dedicated sparing is more costly than homogeneous extraction of a t&ti... View full abstract»

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  • A low power based partitioning and binding technique for single chip application specific DSP architectures

    Publication Year: 1997, Page(s):350 - 361
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimizing the switching activity on the functional units as well as the global buses. The main focus of the developed method is minimizing the power during partitioning and binding phases o... View full abstract»

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  • Ethernet switching-the enabling technology of SOHO implementation

    Publication Year: 1997, Page(s):229 - 236
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    Ethernet switching is an important networking technology that breaks the bandwidth bottleneck in the LAN environment. This technology is being feverishly exploited for the implementation of Intranets in Corporate America. In the long term, Ethernet switching will be the enabling technology for SOHO (Small Office and Home Office) implementation in the 21st Century. An Ethernet switch implemented wi... View full abstract»

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  • Enhancement of MCM testability using an embedded reconfigurable FPGA

    Publication Year: 1997, Page(s):165 - 173
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    The testability of an MCM can be enhanced significantly for very little cost whenever a reprogrammable FPGA component that is already embedded in the MCM for functionality is utilized for diagnostics. This approach can have some of the characteristics of a smart substrate which uses the scan cell beside-the-signal-path (BSP) methodology. The design and implementation of an MCM with this capability... View full abstract»

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