Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors

14-16 July 1997

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  • Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (301 KB)
    Freely Available from IEEE
  • An approach for quantitative analysis of application-specific dataflow architectures

    Publication Year: 1997, Page(s):338 - 349
    Cited by:  Papers (89)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a quantitative way and therefore supports him in the design process to find better performing architectures. The context of our work is video signal processing algorithms which are mapped onto weakly-programmable, coarse-grai... View full abstract»

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  • Index of authors

    Publication Year: 1997, Page(s):539 - 540
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    Freely Available from IEEE
  • Discrete Lagrangian method for optimizing the design of multiplierless QMF filter banks

    Publication Year: 1997, Page(s):529 - 538
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    In this paper, we present a new discrete Lagrangian optimization method for designing multiplierless QMF (quadrature mirror filter) filter banks. In multiplierless QMF filter banks, filter coefficients are powers-of-two (PO2) where numbers are represented as sums or differences of powers of two (also cabled Canonical Signed Digit-CSD-representation), and multiplications can be carried out as addit... View full abstract»

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  • An optimized coefficient update processor for high-throughput adaptive equalizers

    Publication Year: 1997, Page(s):519 - 528
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    A processor for the adaptation of the coefficients in high throughput adaptive equalizers is presented. The accumulation operation-fundamental basis of the adaptation process-is split into two steps: A fine-grain carry-save accumulation with time sharing factor 2 collects the products of estimated error and input symbols over a block length of 16 input symbols and operates at twice the symbol rate... View full abstract»

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  • Low latency word serial CORDIC

    Publication Year: 1997, Page(s):124 - 131
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    In this paper we present a modification of the CORDIC algorithm which reduces the number of iterations almost to half by merging two successive iterations of the basic algorithm. The two coefficients per iteration are obtained with only a small increase in the cycle time by estimating one of the coefficients. A correcting iteration method is used to correct the possible errors produced by the esti... View full abstract»

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  • Optimized software synthesis for synchronous dataflow

    Publication Year: 1997, Page(s):250 - 262
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    This paper reviews a set of techniques for compiling dataflow-based, graphical programs for digital signal processing (DSP) applications into efficient implementations on programmable digital signal processors. This is a critical problem because programmable digital signal processors have very limited amounts of on-chip memory and the speed power, and financial cost penalties for using off-chip me... View full abstract»

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  • An efficient video decoder design for MPEG-2 MP@ML

    Publication Year: 1997, Page(s):509 - 518
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    In this paper, we present an efficient MPEG-2 video decoder architecture design to meet MP@ML real-time decoding requirement. The overall architecture, as well as the design of the major function-specific processing blocks, such as the variable-length decoder, the inverse 2-D discrete cosine transform unit, and the motion compensation unit, are discussed. A hierarchical and distributed controller ... View full abstract»

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  • Three-dimensional orthogonal tile sizing problem : mathematical programming approach

    Publication Year: 1997, Page(s):209 - 218
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    We discuss in this paper the problem of finding the optimal tiling transformation of three-dimensional uniform recurrences on a two-dimensional torus/grid of distributed-memory general-purpose machines. We show that even for the simplest case of recurrences which allows for such transformation, the corresponding problem of minimizing the total running time is a non-trivial non-linear integer progr... View full abstract»

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  • Design methodology for digital signal processing

    Publication Year: 1997, Page(s):468 - 477
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    Improvements in semiconductor integration density and the resulting problem of having to manage designs of increasing complexity is an old one, but still current. The new challenge lies in a new level of architecture heterogeneity, e.g. mixing hard-wired digital circuits with software programmed signal processors on one die. Hence, we are moving by one level of abstraction from semi-custom standar... View full abstract»

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  • Processor elements for the standard cell implementation of residue number systems

    Publication Year: 1997, Page(s):116 - 123
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    In this article processor elements for the effective implementation of standard cell circuits based on residue number systems (RNS) are presented. Two new processors are proposed helping to reduce the hardware requirements of the implementations. Following a new strategy for implementation a comparison between other circuits discussed in past prove the new method and cells to lead to faster and sm... View full abstract»

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  • Libraries of schedule-free operators in Alpha

    Publication Year: 1997, Page(s):239 - 248
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper presents a method, based on the formalism of affine recurrence equations, for the synthesis of digital circuits exploiting parallelism at the bit-level. In the initial specification of a numerical algorithm, the arithmetic operators are replaced with their yet unscheduled (schedule-free) binary implementation as recurrence equations. This allows a bit-level dependency analysis yielding ... View full abstract»

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  • An efficient architecture for the in place fast cosine transform

    Publication Year: 1997, Page(s):499 - 508
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The cosine transform (DCT) is in the core of image encoding and compression applications. We present a new architecture to efficiently compute the fast direct and inverse cosine transform which is based on reordering the butterflies after their computation. The designed architecture exploits locality, allowing pipelining between stages and saving memory (in place). The result is an efficient archi... View full abstract»

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  • Determination of the processor functionality in the design of processor arrays

    Publication Year: 1997, Page(s):199 - 208
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    In this paper the inclusion of hardware constraints into the design of massively parallel processor arrays is considered. We propose an algorithm which determines an optimal scheduling function as well as the selection of components which have to be implemented in one processor of a processor array. The arising optimization problem is formulated as an integer linear program which also takes the ne... View full abstract»

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  • PART: a partitioning tool for efficient use of distributed systems

    Publication Year: 1997, Page(s):328 - 337
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    The interconnection of geographically distributed supercomputers via high-speed networks allows users to access the needed compute power for large-scale, complex applications. For efficient use of such systems, the variance in processor performance and network (i.e., interconnection network versus wide area network) performance must be considered. In this paper, we present a decomposition tool, ca... View full abstract»

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  • ADPCM codec: from system level description to versatile HDL model

    Publication Year: 1997, Page(s):458 - 467
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Due to the rapid increase in the system complexity of modern telecommunication products, two main challenges exist for a system design flow meeting the arising demands: 1) provide a platform for fast algorithmic and architectural design exploration and optimization from system to gate level, which guarantees high quality of results (QoR) and enables full and seamless design verification; 2) provid... View full abstract»

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  • New arithmetic coder/decoder architectures based on pipelining

    Publication Year: 1997, Page(s):106 - 115
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    In this paper we present new VLSI architectures for the arithmetic encoding and decoding of multilevel images. In these algorithms the speed is limited by their recursive natures and the arithmetic and memory access operations. They become specially critical in the case of decoding. In order to reduce the cycle length we propose working with two executions of the algorithm which alternate in the u... View full abstract»

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  • Efficient implementation of rotation operations for high performance QRD-RLS filtering

    Publication Year: 1997, Page(s):162 - 174
    Cited by:  Papers (11)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (740 KB)

    In this paper we present practical techniques for implementing Givens rotations based on the well-known CORDIC algorithm. Rotations are the basic operation in many high performance adaptive filtering schemes as well as numerous other advanced signal processing algorithms relying on matrix decompositions. To improve the efficiency of these methods, we propose to use “approximate rotations&rdq... View full abstract»

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  • Heterogeneous multiprocessor scheduling and allocation using evolutionary algorithms

    Publication Year: 1997, Page(s):294 - 303
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    We propose a novel stochastic approach for the problem of multiprocessor scheduling and allocation under timing and resource constraints using an evolutionary algorithm (EA). For composite schemes of DSP algorithms a compact problem encoding has been developed with emphasis on the allocation/binding part of the problem as well as an efficient problem transformation-decoding scheme in order to avoi... View full abstract»

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  • A linear array parallel image processor: SliM-II

    Publication Year: 1997, Page(s):34 - 41
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper describes architectures and design of a general purpose parallel image processor chip called a SliM-II Image Processor. The chip has a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives 1.92 GIPS. SIiM-II can greatly reduce the inter-PE communication overhead, due to the idea of sliding that is overlapping inter-PE communication with ... View full abstract»

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  • A modular element for shared buffer ATM switch fabrics

    Publication Year: 1997, Page(s):432 - 436
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    This paper presents the architecture of a modular element for the design of shared buffer ATM switch fabrics. The component is designed for deployment in a bit-sliced approach, and includes mechanisms to allow the number of elements in the fabric to be matched to the required aggregate bandwidth of the switch. All of the input ports must be synchronized to a Start of Cell input signal; the output ... View full abstract»

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  • Tiling with limited resources

    Publication Year: 1997, Page(s):229 - 238
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to the mapping and scheduling of the tiles on to physical processors. We present several new results in the context of limited computational resources, and assuming communication-computation overlap. In particular, under som... View full abstract»

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  • Implementation of orthogonal wavelet transforms and their applications

    Publication Year: 1997, Page(s):489 - 498
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    In this paper the efficient implementation of different types of orthogonal wavelet transforms with respect to practical applications is discussed. Orthogonal single-wavelet transforms being based on one scaling function and one wavelet function are used for denosing of signals. Orthogonal multiwavelets are based on several scaling functions and several wavelets. Since they allow properties like r... View full abstract»

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  • A logical framework to prove properties of ALPHA programs

    Publication Year: 1997, Page(s):187 - 198
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    We present an assertional approach to prove properties of ALPHA programs. ALPHA is a functional language based on affine recurrence equations. We first present two kinds of operational semantics for ALPHA together with some equivalence and confluence properties of these semantics. We then present an attempt to provide ALPHA with an external logical framework. We therefore define a proof method bas... View full abstract»

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  • Performance model of the Argonne Voyager multimedia server

    Publication Year: 1997, Page(s):316 - 327
    Cited by:  Papers (2)  |  Patents (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    The Argonne Voyager Multimedia Server is being developed in the Futures Lab of the Mathematics and Computer Science Division at Argonne National Laboratory. As a network based service for recording and playing multimedia streams, it is important that the Voyager system be capable of sustaining certain minimal levels of performance in order for it to be a viable system. In this article, we examine ... View full abstract»

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