IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • May 2018

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  • Table of contents

    Publication Year: 2018, Page(s):C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2018, Page(s): C2
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  • HDL-Based Synthesis System With Debugger for Current-Mode FPAA

    Publication Year: 2018, Page(s):915 - 926
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2459 KB) | HTML iconHTML

    The study demonstrates original environment for synthesizing and implementing current-mode analog circuits in the field programmable analog array (FPAA) technology. The described approach is inspired by existing solutions for digital circuits, implemented using a field programmable gate array. The tools are compatible with the existing hardware architecture description standards (VHDL-AMS, HSPICE)... View full abstract»

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  • SD-PUF: Spliced Digital Physical Unclonable Function

    Publication Year: 2018, Page(s):927 - 940
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1946 KB) | HTML iconHTML

    Digital circuit physical unclonable function (PUF) has been attracting attentions for the merits of resilience to the environmental and operational variations that analog PUFs suffer from. Existing state-of-the-art digital circuit PUFs, however, are either hybrid of analog-digital circuits which are still under the shadow of vulnerability, or impractical for real-world applications. In this paper,... View full abstract»

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  • Chip Temperature Optimization for Dark Silicon Many-Core Systems

    Publication Year: 2018, Page(s):941 - 953
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2498 KB) | HTML iconHTML

    In the dark silicon era, a fundamental problem is given a real-time computation demand, how to determine if an on-chip multiprocessor system is able to accept this demand and to maintain its reliability by keeping every core within a safe temperature range. In this paper, a practical thermal model is described for quick chip temperature prediction. Integrated with the thermal model, we present a m... View full abstract»

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  • Exact Interference of Tasks With Variable Rate-Dependent Behavior

    Publication Year: 2018, Page(s):954 - 967
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1876 KB) | HTML iconHTML

    In embedded real-time systems, the schedulability analysis is an important method to verify whether the real-time constraints are satisfied. Especially, engine control systems in the automotive industry are particular challenging regarding their real-time analysis. Some of the tasks of such systems are triggered at predetermined angular values of the crankshaft. Thus, the frequency of activation i... View full abstract»

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  • Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips

    Publication Year: 2018, Page(s):968 - 981
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3418 KB) | HTML iconHTML

    A digital microfluidic biochip (DMFB) is an attractive platform for immunoassays, point-of-care clinical diagnostics, DNA sequencing, and other laboratory procedures in biochemistry. More recently, DMFBs based on a micro-electrode-dot-array (MEDA) architecture have been proposed, and droplet manipulations on MEDA biochips have also been experimentally demonstrated. In order to ensure robust fluidi... View full abstract»

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  • Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing

    Publication Year: 2018, Page(s):982 - 995
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3400 KB) | HTML iconHTML

    Ultralow-power embedded systems have recently started the move to multicore designs. Aggressive voltage scaling techniques have the potential to reduce the power consumption within the admitted envelope, but memory operations on standard six-transistor static RAM (6T-SRAM) cells become unreliable at low voltages. While standard cell memory (SCM) overcomes this limitation, it has much lower area de... View full abstract»

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  • One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic

    Publication Year: 2018, Page(s):996 - 1008
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1796 KB) | HTML iconHTML

    Reversible computation is a heavily investigated emerging technology due to its promising characteristics in low-power design, its application in quantum computations, and several further application areas. The currently established functional synthesis flow for reversible circuits is composed of two distinct steps. First, an embedding process is conducted which makes nonunique output patterns dis... View full abstract»

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  • MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System

    Publication Year: 2018, Page(s):1009 - 1022
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2292 KB) | HTML iconHTML

    Memristor-based computation provides a promising solution to boost the power efficiency of the neuromorphic computing system. However, a behavior-level memristor-based neuromorphic computing simulator, which can model the performance and realize an early stage design space exploration, is still missing. In this paper, we propose a simulation platform for the memristor-based neuromorphic system, ca... View full abstract»

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  • A Simple and Effective Heuristic Method for Threshold Logic Identification

    Publication Year: 2018, Page(s):1023 - 1036
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2474 KB) | HTML iconHTML

    In this paper, a straightforward and effective method to identify threshold logic function (TLF) is presented. Threshold logic is a promising alternative to conventional Boolean logic due to its suitability for emerging technologies, like memristors, quantum-dot cellular automata, resonant tunneling device, and spintronic devices. Identification and synthesis of TLF are essential tasks in a design... View full abstract»

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  • Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation

    Publication Year: 2018, Page(s):1037 - 1049
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2364 KB) | HTML iconHTML

    The memristor-based memory cell design is getting renewed attention in recent years due to its high speed and low power consumption. This paper aims at designing a novel hybrid memory cell incorporating a minimum number of transistors for a rapid bidirectional write operation. The read stability is one of the key elements for high efficiency and superior performance in memory. The memory cell in t... View full abstract»

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  • MCXplore: Automating the Validation Process of DRAM Memory Controller Designs

    Publication Year: 2018, Page(s):1050 - 1063
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4080 KB) | HTML iconHTML

    We present an automated framework for the validation of memory controllers (MCs) called MCXplore. In developing this framework, we construct formal models for memory requests and command interactions. MCXplore enables validation engineers to define their test plans precisely using temporal logic specifications. We use the NuSMV model-checker to generate counterexa... View full abstract»

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  • Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress

    Publication Year: 2018, Page(s):1064 - 1075
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1442 KB) | HTML iconHTML

    Run-time solutions based on online monitoring and adaptation are required for resilience in nanoscale integrated circuits, as design-time solutions and guard bands are no longer sufficient. Bias temperature instability-induced transistor aging, one of the major reliability threats in nanoscale very large scale integration, degrades path delay over time and may lead to timing failures. Chip health ... View full abstract»

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  • Bit-Flip Detection-Driven Selection of Trace Signals

    Publication Year: 2018, Page(s):1076 - 1089
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2323 KB) | HTML iconHTML

    Since integrating memory blocks on-chip became affordable, embedded logic analysis has been used extensively for post-silicon validation and debugging. Deciding at design time which signals to be traceable at the post-silicon phase, has been posed as an algorithmic problem a decade ago. The primary focus of the subsequent approaches on this topic was to restore as much data as possible within a so... View full abstract»

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  • On Probability of Detection Lossless Concurrent Error Detection Based on Implications

    Publication Year: 2018, Page(s):1090 - 1103
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2336 KB) | HTML iconHTML

    In recent years, a new concurrent error detection method by using invariant relationships inside a circuit, called implications, has been proposed. Algorithms have also been developed to reduce the total number of required implications so as to minimize the incurred area overhead due to implication checking logic. This implication reduction process, however, would result in degradation on the prob... View full abstract»

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  • PUF-FSM: A Controlled Strong PUF

    Publication Year: 2018, Page(s):1104 - 1108
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (449 KB) | HTML iconHTML

    Existing strong controlled physical unclonable function (PUF) designs are built to resist modeling attacks and they deal with noisy PUF responses by exploiting error correction logic. These designs are burdened by the costs of the error correction logic and information shown to leak through the associated helper data for assisting error corrections; leaving the design vulnerable to fault attacks o... View full abstract»

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  • A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation

    Publication Year: 2018, Page(s):1109 - 1113
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (693 KB) | HTML iconHTML

    This paper proposes a new partial scan approach in which the problem of selecting flip-flops in partial scan designs is converted to the balanced graph transformation problem based on an integer linear programming formulation. The complexity of the problem is analyzed and a scalable approach is proposed to deal with complicated circuits. Experimental results on a set of benchmark circuits show tha... View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2018, Page(s): 1114
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  • Introducing IEEE Collabratec

    Publication Year: 2018, Page(s): 1115
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  • IEEE Access

    Publication Year: 2018, Page(s): 1116
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  • IEEE Open Access Publishing

    Publication Year: 2018, Page(s): 1117
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  • Learning Has No Boundaries

    Publication Year: 2018, Page(s): 1118
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2018, Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu