2nd International Conference on ASIC

21-24 Oct. 1996

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Displaying Results 1 - 25 of 115
  • Proceedings of 2nd International Conference on ASIC

    Publication Year: 1996
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    Freely Available from IEEE
  • Structured Methods Applied to CAD Design Flows

    Publication Year: 1996, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB)

    First Page of the Article
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  • Author index

    Publication Year: 1996, Page(s):444 - 447
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    Freely Available from IEEE
  • ASICs design for an MTD radar

    Publication Year: 1996, Page(s):69 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    In an MTD (Moving Target Detect) radar, the digital signal processing is implemented by some real-time processing pipelines which consist of ASICs and FIFO or dual-port memory. We designed six ASICs with Xilinx FPGA, including the clutter-map unit former, the moving target signal extractor, the video signal integrator and the CFAR (Constant False Alarm Rate) operator. While all the timing and cont... View full abstract»

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  • VLSI implementation of the SS7 TCAP

    Publication Year: 1996, Page(s):66 - 68
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    The Transaction Capabilities Application Part (TCAP) is the most recent addition to the Signaling System Number 7 (SS7), an open-ended common channel signaling standard that can be used over a variety of digital circuit-switched networks, in particular, ISDN. In this paper, we present an efficient VLSI implementation of TCAP that was obtained using state-of-the-art logic design and verification to... View full abstract»

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  • The architecture of fuzzy PID gain conditioner and its FPGA prototype implementation

    Publication Year: 1996, Page(s):61 - 65
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Tuning the parameters of PID controller is very important in process control. This paper proposes a FPGC (Fuzzy PID Gain Conditioner) algorithm, a method based on fuzzy control, which tunes the PID controller online. The VLSI architecture of the algorithm is presented in this paper. It can not only realize the algorithms effectively but also improve the performance of the controller significantly.... View full abstract»

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  • Verification by behavioral modeling-a multiprocessor system case

    Publication Year: 1996, Page(s):43 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    Behavioral modeling has many applications in design and verification of computer systems, such as performance study, logic design, test vector generation, verifications and bring-ups, etc. In this paper, a verification scheme for a cache-coherent multiprocessor system using behavioral modeling is presented. A behavioral model and a RTL design model are both driven with the same test cases. By comp... View full abstract»

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  • VHDL description for SDH system simulation and circuit synthesis

    Publication Year: 1996, Page(s):93 - 95
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    This paper presents a specific system architecture that was developed to define a set of circuits required to build a complete SDH (Synchronous Digital Hierarchy) system interfacing respectively with 2 Mbits/s, 34 Mbits/s and 139 Mbits/s PDH (Plesiochronous Digital Hierarchy) networks. The design methodology is based on high level description of complete SDH nodes in order to meet different object... View full abstract»

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  • Research of a Chinese terminal I/O port ASIC

    Publication Year: 1996, Page(s):191 - 193
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    To provide system support for the I/O functions of a Chinese computer terminal, an ASIC with one parallel port, three serial ports, a baud rate generator and two user-controlled ports has been studied and developed. Such a chip can be used to create a multifunction I/O card, or be added to an interface board in some instruments with data I/O functions View full abstract»

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  • A new bipolar op-amp IC synthesis approach

    Publication Year: 1996, Page(s):57 - 60
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    Bipolar op-amp IC modules with a simple circuit structure are difficult to design for a wide range of design specifications, due to strong correlations between transistor parameters. As a result, bipolar op-amps are commonly designed resorting to complicated circuit structures which result in large chip area and high fabrication cost. We have developed a new synthesis approach which can generate b... View full abstract»

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  • Combinational ATPG acceleration by dynamic circuit partition

    Publication Year: 1996, Page(s):413 - 416
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    If no FOS exists in the circuit under test, the execution time of DTM and STM linearly increase proportional to circuit size. The non-linear factors in the algorithm are introduced by FOSs. To limit the affection of FOS's as small as possible, a technique called Dynamic Search Space Reduction is introduced in this paper and only the FOSs who have more then two branches in the sensitive region have... View full abstract»

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  • Verification-oriented MBDD design for digital circuits

    Publication Year: 1996, Page(s):39 - 42
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    Efficient manipulation of Boolean functions is an important component of many CAD tasks. In this paper, a new and practical State Transition Graph (STG) construction method, which is based on the appending operation from standard gate MBDD (Max/Min Standard BDD Construction) is proposed. Obviously, a reduced STG in which the inputs and states are collapsed, is obtained. Finally, several experiment... View full abstract»

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  • A methodology for high level synthesis of high performance DSP structures targetting FPGAs

    Publication Year: 1996, Page(s):89 - 92
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    High level synthesis transforms a given behavioral specification into a register transfer level that can implement the given behavior. In this paper a novel technique that combines heuristics and mathematical programming formulation of the synthesis problem is introduced. This technique exploits features of the implementation hardware FPGAs and explore larger solution space than previous approache... View full abstract»

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  • Design and analysis of loop code recognition circuits

    Publication Year: 1996, Page(s):187 - 190
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    This paper introduces the design of some circuits that can recognize loop code from an input code stream. The loop code in the stream can be arbitrary or a template specified by the user. We especially discuss the design method of these circuits, along with some simulation results View full abstract»

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  • System level test generation and fault simulation for VLSI circuits

    Publication Year: 1996, Page(s):396 - 399
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    This paper presents a new concept in VLSI test domain: System Level Test Generation and Fault Simulation. In the paper, we describe the process of VLSI circuit design, discuss abstraction of information processed by the circuit, and address the outline of system level test generation and fault simulation View full abstract»

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  • An FPGA approach of channel decoder for DAB test receiver

    Publication Year: 1996, Page(s):214 - 217
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The Digital Audio Broadcasting (DAB) system promises to provide CD-quality sounds and flexible data services to mobile, portable and fixed receivers. In order to achieve high quality in multipath environment, a complicated channel coding and modulation scheme is adopted. This paper presents a channel decoding architecture for DAB test receiver, which accomplishes the functions including program se... View full abstract»

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  • ISP solution for radar video processing: resolution improvement and side-lobe cancellation

    Publication Year: 1996, Page(s):53 - 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    A navigation radar video processing algorithm is implemented, which can improve both range and bearing resolution by 20% and reduce side-lobe level by 6 dB or more, theoretically. An In-System Programmable (ISP) HDPLD (or CPLD) design scheme is given along with logic details and timing analysis View full abstract»

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  • ASIC design considerations for address vector generation in memory test system

    Publication Year: 1996, Page(s):409 - 412
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    In this paper an application-specific integrated circuit (ASIC) is presented for the generation of address vector of memory test system View full abstract»

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  • A dual token ring and Ethernet LAN interface chip

    Publication Year: 1996, Page(s):167 - 170
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    A CMOS LAN interface chip that combines the physical layer functions for both the token ring and Ethernet networks is described. The 4/16 mbps Token Ring interface exceeds the jitter tolerance (0.5 ns/UI) and accumulated phase slope (0.25 ns/UI) requirements at 16 Mbps of the IEEE 802.5 draft standard for STP/UTP transmission media. The 10 Mbps Ethernet interface supports both the AUI and 10BaseT ... View full abstract»

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  • Pin allocation for clock routing

    Publication Year: 1996, Page(s):35 - 38
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    We present two algorithms for allocating clock pin positions to reduce connection, length while maintaining zero clock skew. For the channel routing case, a graph model is introduced to precisely represent the problem. Based on the model, a clock tree with minimal length, depth and skew is obtained. For a given placement, the depth of the clock tree is proved to be minimal while minimizing the clo... View full abstract»

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  • The design of an ASIC-multiplexer used in digital communication

    Publication Year: 1996, Page(s):284 - 287
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    This paper presents a novel design of communication ASIC multiplexer, which is an asynchronous system with positive code speed justification and consists of about eighty thousand integrated MOSFETs. In the multiplexer, the clocking block and digital locked-loops were designed. The designed system can be used in two different modes: the system allows 2/8 Mb multiplexing function of 8/34 Mb multiple... View full abstract»

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  • Power management in high-level design

    Publication Year: 1996, Page(s):357 - 363
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Power is significant concern for any application that distinguishes itself by battery life (e.g., pagers, cellular phones, etc.), but this is not the only power sensitive market. Power management is just as critical for today's ASIC and IC designers in nearly every market segment. Consider the following: Increased power increases electromigration and reduces reliability in long-life-cycle telecom ... View full abstract»

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  • The algorithm design in the field of structure optimization of logic synthesis

    Publication Year: 1996, Page(s):85 - 88
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    This paper discusses the algorithm design for a special type of structure optimization in the field of logic synthesis. The data structure used inhere is a kind of directed graph. We'll give the algorithm framework on the basis of analysis and comparison. A substantial logic network used as input data can demonstrate the efficiency and the feasibility of the software programmed in this algorithm View full abstract»

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  • Digital correlator EPLD design

    Publication Year: 1996, Page(s):183 - 186
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    This paper begins with the imperativeness of applying EPLD technique to digital correlator design of communication systems. On this basis, it explains the relative technical problems existing in the EPLD design of a digital correlator, analyses the hardware resource provided by EPLD and gives a description of an example of design as well as relevant test results. It concludes with several suggesti... View full abstract»

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  • Testing techniques for embedded memories in ASIC

    Publication Year: 1996, Page(s):376 - 379
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    This paper provides a survey of four practical testing techniques for embedded memories in ASIC in industry. The pros and cons of these techniques are studied in terms of area, timing, power, pin count, automation, test speed, test quality and chip testing View full abstract»

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