5-8 Nov. 2006
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Publication Year: 2006, Page(s): i|
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Publication Year: 2006, Page(s): ii|
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Publication Year: 2006, Page(s): iii|
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Publication Year: 2006, Page(s): v|
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Table of contents
Publication Year: 2006, Page(s):1 - 2|
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Visualization Using the Scanning Nonlinear Dielectric Microscopy of Electrons and Holes Localized in the Thin Gate Film of Metal-Oxide-Nitride-Oxide-Semiconductor Type Flash Memory
Publication Year: 2006, Page(s):4 - 11
Cited by: Papers (1)By applying scanning nonlinear dielectric microscopy (SNDM), we identified the position of electrons/holes existing in the gate SiO2-Si3N4-SiO2 (ONO) film of the Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) type flash memory. The electrons were detected in the Si3N4 part of the ONO film. The holes, on the other hand, were found i... View full abstract»
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1/f Noise Analysis of a 75 nm Twin-Flash Technology Non-Volatile Memory Cell
Publication Year: 2006, Page(s):12 - 15Analyzing the electrical degradation of modern flash memory cells by conventional C-Vor charge pumping techniques is hardly possible due to the extremely small gate area. However, 1/f noise measurements can be done since low frequency 1/f noise in the range around 1 Hz produced by stress-generated oxide traps strongly increases in MOSFETs with shrinking area. Here we show that measurements of the ... View full abstract»
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A New Self-Aligned NAND Type SONOS Flash Memory with High Scaling Abilities, Fast Programming/Erase Speeds and Good Data Retention Performances
Publication Year: 2006, Page(s):16 - 20In this paper, we will propose a new NAND type SONOS cell structure with high efficiency Source Side Injection programming and F-N erase. This cell is characterized in high scaling abilities, fast program/erase speeds and very satisfactory data retention performances. In consideration of the threshold voltage saturation of the SONOS cell during erase, we use the modified erase bias configuration, ... View full abstract»
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Eliminating Word Line Bending In Floating Gate NOR Flash Memory To Reduce Array Size and Improve Manufacturability
Publication Year: 2006, Page(s):21 - 25In floating gate (FG) NOR flash memory arrays, word lines (WL) bend at Vss columns to accommodate the Vss contacts. As the memory cell is scaled down, patterning of the WL bending becomes more and more challenging. Furthermore, to ensure that the WL bending does not extend to the adjacent memory cells to cause abnormal electrical characteristics of the adjacent cells, we have... View full abstract»
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EEPROM Compact Model with SILC Simulation Capability
Publication Year: 2006, Page(s):26 - 30
Cited by: Papers (3)The objective of this paper is to present a EEPROM compact model suitable for SILC simulation. The SILC module allows simulating the retention capability of the cell after stress. Test chip array distribution and standard tunnel capacitor are used to extract the SILC module parameters. Thus the extraction procedure is detailed. The description of the complete model is presented. A simulation examp... View full abstract»
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TCAD Modeling and Data of NOR Nanocrystal Memories
Publication Year: 2006, Page(s):31 - 33This work presents TCAD simulations of NOR NC memories performed with commercial tools, which allow for a good understanding of the impact of the localized charge on both electrostatics and dynamics of the cell. The key role of the position of the trapped charges along the channel length on the threshold voltage shift has been put in evidence. Indeed, this result is critical for NOR discrete-trap ... View full abstract»
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Ferroelectric Ultra High-Density Data Storage Based on Scanning Nonlinear Dielectric Microscopy
Publication Year: 2006, Page(s):34 - 39Nano-sized inverted domain dots in ferroelectric materials have potential application in ultrahigh-density rewritable data storage systems. Herein, a data storage system is presented based on scanning non-linear dielectric microscopy and a thin film of ferroelectric single-crystal lithium tantalite. Through domain engineering, we succeeded to form an smallest artificial nano-domain single dot of 5... View full abstract»
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Reliability of three-dimensional ferroelectric capacitor memory-like arrays simultaneously submitted to x-rays and electrical stresses
Publication Year: 2006, Page(s):40 - 44
Cited by: Papers (3) | Patents (2)Future development of Ferroelectric Random Access Memories (FeRAM) requires integration of three-dimensional (3D) ferroelectric capacitors in replacement of usual planar capacitors. This innovative geometry enables the fabrication of highly reliable memory devices with improved sensing signal. In order to target space applications, it is of primary interest to analyze the effects of ionizing radia... View full abstract»
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Magnetic Shadow RAM
Publication Year: 2006, Page(s):45 - 48
Cited by: Papers (4)We propose a new shadow RAM circuit, utilizing magnetic tunnel junctions and an independent-double-gate CMOS technology. A shadow RAM combines a conventional static RAM circuit with a non-volatile "shadow", and provides a means to quickly transfer data between them. Non-volatile magnetic storage offers several advantages over current technology for this application, with unlimited write endurance,... View full abstract»
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Switching Properties in Spin Transper Torque MRAM with sub-5Onm MTJ size
Publication Year: 2006, Page(s):49 - 51
Cited by: Papers (2)Magnetic random access memory using spin-transfer torque effect has been developed with 30 nm sized magnetic tunnel junction (MTJ) cells. In this paper, we will describe the switching properties of sub-50 nm sized MTJ patterned by conventional lithography and etching process. Low switching current density (Jc) of 1.63times106 A/cm2 with 10 ns pulse was achieved by optimizing ... View full abstract»
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Unique Challenges and Solutions in CMOS Compatible NVM
Publication Year: 2006, Page(s):52 - 54
Cited by: Papers (1)CMOS compatible NVM is finding increasing applications that range from a few bits in analog trim applications to kilobits for data or code. CMOS compatibility comes with unique retention and endurance challenges. The floating gate is in direct contact with backend dielectric, which degrades high temperature data retention performance. Drain and well doping profile are not optimized to favor hot ca... View full abstract»
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Characterization of Silicided Polysilicon Fuse Implemented in 65nm Logic CMOS Technology
Publication Year: 2006, Page(s):55 - 57
Cited by: Papers (5) | Patents (46)NiSi electrically programmable fuses (eFUSE) were fabricated and investigated using 65 nm logic CMOS technology. The optimization of fuse program was achieved by analyzing electrical and physical responses of fuse bits for various conditions. Controlled electromigration of Ni during fuse program was identified as a key factor in achieving reliably high post-program fuse resistance. View full abstract»
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A Defect-Tolerant Architecture for Nanoelectronic Resistive Memories
Publication Year: 2006, Page(s):58 - 63
Cited by: Papers (5)We have calculated the useful density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective hybrid (CMOS/nanodevice) resistive memories, as a function of the defective memory cell fraction. The results indicate that the memories with a CMOS/nano pitch ratio close to 3 (which is typical for the current, initial stage of hybrid circuit deve... View full abstract»
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A 4-Mbit Non-Volatile Chalcogenide-Random Access Memory Designed for Space Applications
Publication Year: 2006, Page(s):64 - 70
Cited by: Papers (5)A 4 Mbit non-volatile chalcogenide-random access memory (C-RAMTM) has been designed and fabricated in RH 25, a radiation hardened CMOS technology. The top-down design focused on accommodating chalcogenide process variations and satisfying space system specifications. The optimized band-gap circuit supplies reference current and voltage that meet temperature and voltage requirements. The... View full abstract»
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Integrated Analysis and Design of Phase-Change Random Access Memory (PCRAM) Cells
Publication Year: 2006, Page(s):71 - 75
Cited by: Papers (3)An integrated software for analysis and design of PCRAM cells has been developed. The research focuses on the discussion on electric-thermal -mechanical analyses. The software involves in the materials, geometrical and layer structure design and electric pulse strategy. It aims to provide a powerful tool for structure optimization and failure analysis of PCRAM cells. View full abstract»
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Investigation of Nano-Phase Change for Phase Change Random Access Memory
Publication Year: 2006, Page(s):76 - 80
Cited by: Papers (2)Understanding of the phase change in nano-scale, or so-called nano-phase change, and its related issues are important for its applications on both optical recording and phase change random access memory (PCRAM). Nano-phase change can be classified into thickness-dependent and structure dependent types. For PCRAM device performance, the film thickness-dependent thermal profile and materials' proper... View full abstract»
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Preparation of Oxygen-doped and Nitrogen-doped Ge-Sb-Te System Thin Film for Phase Change Random Access Memory by RF Magnetron Sputtering
Publication Year: 2006, Page(s):81 - 83
Cited by: Patents (2)We prepared oxygen-doped and nitrogen-doped Ge-Sb-Te system thin film by RF magnetron sputtering, and investigated its crystallinity and resistivity with several annealing temperature and oxygen and nitrogen doping content. The test phase change device was fabricated to confirm switching characteristics between crystalline (set) and amorphous (reset) phases. The resistance of nitrogen-doped GST ch... View full abstract»
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Snapback by Hot Filament
Publication Year: 2006, Page(s):84 - 88
Cited by: Papers (2)A simulation procedure using the conventional thermal-electric finite element method for the phase change memory has been developed. By introducing a defect on the amorphous chalcogenide of a reset phase change memory, the snapback by hot filament due to thermal runaway has been investigated by the numerical simulations with three-dimensional model. View full abstract»
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Resistance Switching Characteristics of Metal Oxide and Schottky Junction for Nonvolatile Memory Applications
Publication Year: 2006, Page(s):89 - 93
Cited by: Papers (2)We evaluated the resistive switching effect of the polycrystalline oxide (Nb2O5, ZrOx and Cr-SrTiO3) fabricated by reactive sputtering and PLD. It shows a well-developed resistive switching behavior. The reproducible resistance switching cycles were observed and the resistance ratio was as high as 50~100 times. The resistance switching was observed under... View full abstract»
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Microstructure and resistance switching in NiO binary oxide films obtained from Ni oxidation
Publication Year: 2006, Page(s):94 - 99
Cited by: Papers (2) | Patents (38)Oxide Resistive Random Access Memories (OxRRAM) are discussed for future high density non volatile memory chips. NiO and other simple binary transition metal oxides (such as TiO2, HfO2 or ZrO2) have recently attracted much attention. In most cases, polycrystalline oxide films are deposited by reactive sputtering on conductive substrates to form bi-stable Metal/Resi... View full abstract»