Proceedings International Conference on Computer Design. VLSI in Computers and Processors

7-9 Oct. 1996

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  • Proceedings International Conference on Computer Design. VLSI in Computers and Processors

    Publication Year: 1996
    Request permission for commercial reuse | PDF file iconPDF (517 KB)
    Freely Available from IEEE
  • Evaluation of high speed LAN protocols as multimedia carriers

    Publication Year: 1996, Page(s):93 - 98
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (533 KB)

    The complexity of multimedia applications, which integrate a variety of information sources, such as audio, voice, graphics, images, animation, and full-motion video, into a wide range of applications, stresses all the components of computer and communication systems. Many new ideas have been proposed and implemented for advanced LAN (Local Area Network) protocols in order to support multimedia ne... View full abstract»

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  • Index of authors

    Publication Year: 1996, Page(s):587 - 589
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    Freely Available from IEEE
  • DNA computations can have global memory

    Publication Year: 1996, Page(s):344 - 347
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Ever since Adleman's seminal paper (1994) there has been a flood of ideas on how one could use DNA to compute. There have been many papers on using DNA to solve various computational problems. At the top-most level all these papers use DNA in the same way. Each strand of DNA encodes the state of a processor. Each processor operates independently: there is no communication from one processor to ano... View full abstract»

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  • Low voltage and low power: how low can you go?

    Publication Year: 1996
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    Power management is an important design issue. For mobile electronics, the motivation is to extend battery life. For desktop systems, the design goal is to reduce audible noise from cooling fans which are a cause of annoyance, and to reduce the heat release in closed environments. For large systems, the motivation is to hold the packaging cost down. In communication applications, the limit on RF p... View full abstract»

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  • Multiway partitioner for high performance FPGA based board architectures

    Publication Year: 1996, Page(s):579 - 585
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    Field-programmable gate array based board architectures are becoming fairly common for rapid prototyping and custom computing. In order to map large designs on multiple FPGA based boards, the design has to be partitioned into two or more segments. In this paper we describe the architecture, constraints, and a solution to the area and pin constrained partitioning problem. Our effort is directed tow... View full abstract»

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  • Branch-directed and stride-based data cache prefetching

    Publication Year: 1996, Page(s):225 - 230
    Cited by:  Papers (4)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    Cache memories are commonly used to reduce the performance gap between microprocessor and memory technology. To increase the chances that a cache can provide instructions and data when requested, prefetching can be employed. Prefetching attempts to prime the cache with instructions and data which will be accessed in the near future. The work presented describes a prefetching algorithm which ties d... View full abstract»

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  • A compact neural network based CDMA receiver for multimedia wireless communication

    Publication Year: 1996, Page(s):99 - 103
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A compact neural network receiver to process code division multiple access (CDMA) communication is presented. In CDMA system, near-far problem is a major impediment for the performance of a conventional detector. By using a compact neural network with hardware annealing function and combinatorial optimization technique, an optimal multiuser detector can be implemented. The algorithm and architectu... View full abstract»

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  • Clock-delayed domino for adder and combinational logic design

    Publication Year: 1996, Page(s):332 - 337
    Cited by:  Papers (23)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    An innovative dynamic logic family, clock-delayed (CD) domino, was developed to provide gates with either inverting or non-inverting outputs, and the high speed and layout compactness of dynamic logic. The characteristics of CD domino are demonstrated in two carry lookahead adder designs and three MCNC combinational logic benchmark circuits. The CD domino designs are compared to designs using stat... View full abstract»

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  • An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design

    Publication Year: 1996, Page(s):572 - 578
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    A novel algorithm, named SeqMapII, of technology mapping with retiming for optimal clock period for K-LUT based FPGAs was recently proposed by P. Pan and C.L. Liu (1996). The time complexity of their algorithm, however, is O(K3n4 log(Kn2) log n) for sequential circuits with n gates, which is too high for medium and large size designs in practice. In this paper, we ... View full abstract»

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  • Behavioral verification of an ATM switch fabric using implicit abstract state enumeration

    Publication Year: 1996, Page(s):20 - 26
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB)

    We investigate equivalence checking of the RTL hardware implementation of the Cambridge Fairisle Asynchronous Transfer Mode (ATM) 4 by 4 switch fabric against a high-level behavioral specification which has unrestricted frame size, cell length and word width. The verification is based on the reachability analysis of the product machine of the implementation and the specification, both modeled as A... View full abstract»

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  • Distributed binary decision diagrams for verification of large circuits

    Publication Year: 1996, Page(s):365 - 370
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Binary Decision Diagrams (BDDs) are widely used for efficiently representing logic designs and for verifying their equivalence. However, they often require large amounts of memory even for relatively small circuits. This paper presents a new mechanism for alleviating the memory consumption problem by exploiting the memory available in a cluster of workstations. The memory required for a BDD node m... View full abstract»

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  • Profile-driven generation of trace samples

    Publication Year: 1996, Page(s):217 - 224
    Cited by:  Papers (6)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    Trace driven simulation is a common technique for evaluating different machine design options. Since the computing resources needed for simulation depend on the size of the trace, it is not always practical to use the complete trace of an application for simulation. This paper proposes a new technique, profile-driven sampling, for obtaining a reduced trace that is representative of the complete tr... View full abstract»

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  • VLIW-processors under periodic real time constraints

    Publication Year: 1996, Page(s):191 - 199
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1004 KB)

    This paper deals with the cyclo-static (periodic) scheduling of iterative instruction sequences on VLIW-processor architectures, in the case when the period is imposed (periodic real time constraints). This problem naturally arises when designing VLIW-processor architectures as I/O interfaces between cyclo-static-processor arrays and the external world. Three important mapping problems related to ... View full abstract»

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  • Design methodologies for tolerating cell and interconnect faults in FPGAs

    Publication Year: 1996, Page(s):326 - 331
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    Significant increases in chip yield can result if faulty logic cells and wiring in field programmable gate arrays (FPGAs) can be isolated from the remainder of the circuitry to retain a completely usable chip. Utilizing the principle of node-covering, a routing discipline has been developed that allows each logic cell in an FPGA to cover-to be able to replace-its neighbor in a row. An FPGA is fact... View full abstract»

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  • Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers

    Publication Year: 1996, Page(s):492 - 499
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    The paper presents a systematic theoretical approach for the analysis of bounds on power consumption in Baugh-Wooley, binary tree and Wallace tree multipliers. This is achieved by first developing state transition diagrams (STDs) for the sub circuits making up the multipliers. The STD is comprised of states and edges, with the edges representing a transition (switching activity) from one state to ... View full abstract»

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  • Modeling the difficulty of sequential automatic test pattern generation

    Publication Year: 1996, Page(s):261 - 271
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB)

    This paper introduces a model which describes the cost of automatic test pattern generation for (non-scan) sequential logic in terms of attributes of the circuit under test. This model addresses a core issue involved in integrated circuit design and test trade-offs, and can be used to evaluate the cost effectiveness of potential design-for-testability (DFT) techniques. This knowledge can also be u... View full abstract»

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  • Modeling the technology impact on the design of a two-level multicomputer interconnection network

    Publication Year: 1996, Page(s):165 - 169
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    The rapid advance of VLSI and packaging technologies has a significant impact on system architecture. In this paper, an analytical model is used to explore the design space of interconnection networks for a 4,096 node processing system incorporating multi-node chips packaged on a single MCM substrate. Possible designs are evaluated for a two-level interconnect with separate k-ary n-cube networks f... View full abstract»

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  • FPGA module minimization

    Publication Year: 1996, Page(s):566 - 571
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    We examine the problem of minimizing the number of modules in an FPGA with combinational and sequential modules (like the C-modules and S-modules of the ACT2 and ACTS architectures). The constraint is that a combinational module can be combined with one flip-flop in a single sequential module, only if the combinational module drives no other combinational modules. We show that the problem of rearr... View full abstract»

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  • Early quantification and partitioned transition relations

    Publication Year: 1996, Page(s):12 - 19
    Cited by:  Papers (20)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB)

    Hardware systems are generally specified as a set of interacting finite state machines (FSMs). An important problem in formal verification using Binary Decision Diagrams (BDDs) is forming the transition relation of the product machine. This problem reduces to conjuncting (or multiplying) the BDDs representing the transition relations of the individual machines, and then existentially quantifying o... View full abstract»

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  • An integrated microspacecraft avionics architecture using 3D multichip module building blocks

    Publication Year: 1996, Page(s):141 - 144
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    In this paper, we describe current results from work in progress on the continued miniaturization of all spacecraft electronics into a single avionics system, using building-block elements. Each element is assumed to be a `slice' within a stackable multichip module (MCM) 3D-architecture. The proposed architecture is new for the space community, but, is familiar to the commercial world. That is, we... View full abstract»

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  • Binary decision diagrams on network of workstations

    Publication Year: 1996, Page(s):358 - 364
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    The success of all binary decision diagram (BDD) based synthesis and verification algorithms depend on the ability to efficiently manipulate very large BDDs. We present algorithms for manipulation of very large Binary Decision Diagrams (BDDs) on a network of workstations (NOW). A NOW provides a collection of main memories and disks which can be used effectively to create and manipulate very large ... View full abstract»

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  • Microarchitecture support for reducing branch penalty in a superscaler processor

    Publication Year: 1996, Page(s):208 - 216
    Cited by:  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    This paper describes the microarchitecture of the 32-bit superscalar microprocessor GMICRO/400 with simple prejump mechanisms and its performance evaluation. GMICR0/400 has six stages of instruction execution pipeline and implements a dynamic branch prediction scheme, executing jump instructions in early stages. For dynamic branch predictions, GMICR0/400 contains a 1-Kbit table which holds a singl... View full abstract»

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  • On design of efficient square generator

    Publication Year: 1996, Page(s):506 - 511
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    The product of two numbers A and B can be calculated from A2 and B2. The simplest way for evaluating the squares is the use of ROM look up tables. However the conventional ROM table approaches are limited only for small bit size applications due to the unmanageable increase of the ROM table size. A novel design of square generator using a folding approach is presented to red... View full abstract»

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  • Module generators for a regular analog layout

    Publication Year: 1996, Page(s):280 - 285
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    In general, automatic layout composition techniques based on pre-designed devices facilitate the production of small IC numbers by prefabricating their basic structures. They also enable a high degree of automatic layout synthesis. However for their correct electrical behavior it is essential, that potential problems caused by electro-magnetic compatibility (EMC) are fully considered during the de... View full abstract»

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