[1992] Proceedings 29th ACM/IEEE Design Automation Conference

8-12 June 1992

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  • Proceedings. 29th ACM/IEEE Design Automation Conference (Cat. No.92CH3144-3)

    Publication Year: 1992
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    Freely Available from IEEE
  • Optimal scheduling and allocation of embedded VLSI chips

    Publication Year: 1992, Page(s):116 - 119
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A new integer programming (IP) model is presented for synthesizing high speed embedded VLSI chips. A model is presented for simultaneous scheduling, selecting types of functional units, allocation and determining the clock period. Functional units can be chained, multicycled, or pipelined, with different speed and area characteristics. A large number of optimal architectures, satisfying area, spee... View full abstract»

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  • Optimal allocation and binding in high-level synthesis

    Publication Year: 1992, Page(s):120 - 123
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The authors present an integer linear program (ILP) formulation for the allocation and binding problem in high-level synthesis. Given a behavioral specification and a time-step schedule of operations, the formulation minimizes wiring and multiplexer areas. An ILP model for minimizing multiplexer and wiring areas has been mathematically formulated and optimally solved. The model handles chaining, m... View full abstract»

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  • Time constrained allocation and assignment techniques for high throughput signal processing

    Publication Year: 1992, Page(s):124 - 127
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A technique for the allocation of complex application specific datapaths is presented. The technique is especially suited for the synthesis of application specific architectures for high-throughput signal processing applications. Such applications comprise hierarchical compositions of nested loops and condition blocks. A minimum area set of datapaths is allocated and the available cycle budget is ... View full abstract»

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  • Hierarchical pitchmatching compaction using minimum design

    Publication Year: 1992, Page(s):311 - 317
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    A new hierarchical compactor capable of compacting and pitchmatching hierarchically defined layouts is described. The hierarchical compactor can handle most input hierarchies, including multilevel hierarchies, over the cell routing and cell rotations and reflections. The compactor simultaneously compacts the contents of all the cells of the layout hierarchy maintaining the hierarchy of the input l... View full abstract»

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  • Recurrence equations and the optimization of synchronous logic circuits

    Publication Year: 1992, Page(s):556 - 561
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The authors present a formulation for the problem of optimizing synchronous logic across register boundaries. They describe the degrees of freedom that are the don't-care conditions of an embedded subnetwork by means of sets of execution traces, described implicitly by synchronous recurrence equations. The optimization problem reduces to that of finding minimum-cost solutions to such equations. An... View full abstract»

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  • An engineering environment for hardware/software co-simulation

    Publication Year: 1992, Page(s):129 - 134
    Cited by:  Papers (49)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The authors describe an environment supporting concurrent hardware and software engineering for high performance systems. In place of a conventional bread-boarded prototype, they used distributed communicating processes to allow software and simulated hardware to interact. The Cadence Verilog-XL simulator was extended to enable software debugging and testing using hardware simulation. The environm... View full abstract»

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  • Routing considerations in symbolic layout synthesis

    Publication Year: 1992, Page(s):682 - 686
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The authors discuss routing styles, including a newly proposed hybrid routing style, in basic silicon-level design for a symbolic layout synthesis tool with practical considerations for design rules and process technology. Methods for systematically adding jogs in the layout to achieve high layout quality are proposed. Algorithms for input/output-pin assignment and for pin-ordering routing that ac... View full abstract»

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  • Fuzzy logic approach to placement problem

    Publication Year: 1992, Page(s):153 - 158
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The authors apply fuzzy reasoning to the placement of sea-of-gate arrays. Fuzzy logic is used to optimize a process of decision making in physical design. Multiple objectives such as utilization of area, routability, and timing were considered simultaneously and balanced by fuzzy logic algorithms. The experiments demonstrated that solutions obtained by fuzzy logic were of much better quality than ... View full abstract»

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  • High-level synthesis with pin constraints for multiple-chip designs

    Publication Year: 1992, Page(s):231 - 234
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The authors describe an approach to multi-chip data path synthesis, given a behavorial description which has already been partitioned into a number of clusters, with the feasibility of clusters determined. The problem is divided into interchip connection determination and scheduling. A heuristic search technique is described for interchip connection determination. A pipelined RTL design consisting... View full abstract»

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  • Functional approaches to generating orderings for efficient symbolic representations

    Publication Year: 1992, Page(s):624 - 627
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    The authors present a functional approach to generating orderings for representing functions. They develop a cost function which closely mimics the ordered binary decision diagram operations and can be quickly computed. Using the cost as a metric for an ordering, an annealing procedure was used to arrive at good variable orderings. The results obtained by simulated annealing are compared to orderi... View full abstract»

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  • An integrated approach to realistic worst-case design optimization of MOS analog circuits

    Publication Year: 1992, Page(s):704 - 709
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming p... View full abstract»

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  • Process independent constraint graph compaction

    Publication Year: 1992, Page(s):318 - 322
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    The author describes the DASL symbolic layout system, which is used to create experimental VLSI circuits. The DASL constraint graph compactor requires no user intervention to produce a process-independent design. It also produces results that are electrically correct, e.g., that control the placement of substrate contacts. In other constraint graph compaction if there is nothing to constrain an el... View full abstract»

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  • Finite state machine synthesis with fault tolerant test function

    Publication Year: 1992, Page(s):562 - 567
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The authors propose a new method of synthesizing programmable logic array (PLA)-based finite-state machines with fault tolerant test machines. The procedure allows arbitrary state encoding. This can be exploited to achieve other objectives like minimizing the area of the PLA. Also, they do not assume an explicit reset state, and test generation does not require traversal of state transition progra... View full abstract»

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  • High level synthesis of pipelined instruction set processors and back-end compilers

    Publication Year: 1992, Page(s):135 - 140
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    The authors propose a synthesis methodology for high-performance pipelined instruction set processors. Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of the Advanced Design Automation System (ADAS) which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is ... View full abstract»

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  • Experiments with a performance driven module generator

    Publication Year: 1992, Page(s):687 - 690
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The authors describe a performance-driven module generator (perflex) for efficient generation of fast static combinational CMOS circuit modules. A new flexible CMOS layout style provides the foundation for implementing fast circuits. Timing optimization is performed via transistor sizing, transistor reordering, and the reduction of wiring capacitance on critical paths, all of which are performed i... View full abstract»

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  • Delay fault test generation for scan/hold circuits using Boolean expressions

    Publication Year: 1992, Page(s):159 - 164
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    A new test generation technique for path delay faults in scan/hold type circuits is presented. It uses reduced ordered binary decision diagrams to represent Boolean functions implemented by the subcircuits in a circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit under test and a pair of constraint function... View full abstract»

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  • Partitioning by regularity extraction

    Publication Year: 1992, Page(s):235 - 238
    Cited by:  Papers (36)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The authors present a general methodology for extracting regularity at any level of hierarchy, and explore the problem of digital system partitioning by extraction of regularity. They consider system-level partitioning to demonstrate that regularity can lead to reduced design costs. The digital system is modeled with cyclic directed graphs. A prototype system based on these ideas has been built. S... View full abstract»

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  • At-speed delay testing of synchronous sequential circuits

    Publication Year: 1992, Page(s):177 - 181
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonst... View full abstract»

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  • Inductive verification of iterative systems

    Publication Year: 1992, Page(s):628 - 633
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Recent advances in binary decision diagram (BDD)-based algorithms have brought much larger circuits than before within the reach of verification programs. The authors show how inductive proof procedures can derive information on regular circuits in optimal time, e.g. they can perform reachability analysis in linear time or check the equivalence of two iterative circuits in time independent of the ... View full abstract»

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  • On the circuit implementation problem [combinatorial logic circuits]

    Publication Year: 1992, Page(s):478 - 483
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The authors consider the problem of selecting an implementation of each circuit module from a cell library to satisfy overall delay and area, or delay and power requirements. Two versions of the circuit implementation problem, the basic circuit implementation problem and the general circuit implementation problem, are shown to be NP-hard. A pseudo-polynomial-time algorithm for the basic circuit im... View full abstract»

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  • Circuit enhancement by eliminating long false paths

    Publication Year: 1992, Page(s):249 - 252
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The authors propose to identify and perform logic replacement for a portion; called a segment, of a long path instead of the path itself. This results in less gate and lead duplication and hence reduction in the increase of circuit area. They give sufficient conditions for the choice of segments that can maintain the performance of the circuit. If the restriction on the choice of segments is relax... View full abstract»

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  • Coalgebraic division for multilevel logic synthesis

    Publication Year: 1992, Page(s):438 - 442
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    By introducing two Boolean properties into an algebraic division operation, a subset of Boolean division can be performed with approximately the same complexity as the algebraic division implemented in the misII environment. The extended algebraic division algorithm is called coalgebraic division. The experimental results show that the execution time of coalgebraic division is very close to that o... View full abstract»

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  • Incremental circuit simulation using waveform relaxation

    Publication Year: 1992, Page(s):8 - 11
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Two algorithms were developed using waveform relaxation for the rapid re-simulation of circuits that have been modified slightly compared to a previous simulation run. Both local and global changes can be handled so long as the changes are relatively small. In this approach, the window sizes, step sizes, and final waveforms from a previous simulation were used to drive the incremental simulation. ... View full abstract»

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  • Multipole-accelerated 3-D capacitance extraction algorithms for structures with conformal dielectrics

    Publication Year: 1992, Page(s):710 - 715
    Cited by:  Papers (9)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The new three-dimensional capacitance calculation program FASTCAP2 is described. Like the earlier program FASTCAP, FASTCAP2 is based on a multipole-accelerated algorithm that is efficient enough to allow three-dimensional capacitance calculations to be part of an iterative design process. FASTCAP2 differs from FASTCAP in that it was able to analyze problems with multiple-dielectrics, thus extendin... View full abstract»

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