Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

7-10 Sept. 1992

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  • Multi-kernel simulation description within VHDL

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Summary form only given. The authors describe ongoing work on multikernel description facilities within VHSIC hardware description language (VHDL) which is performed in the scope of ECIP (European CAD Integration Project). The motivation, aims, and scope of the work are outlined.<> View full abstract»

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  • Selected aspects of component modeling

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (86 KB)

    Summary form only given. VHSIC hardware description language (VHDL) models should be defined along precise guidelines in order to guarantee their compatibility and efficiency. The author reports on the generation of component models and the quantitative analysis of models.<> View full abstract»

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  • Towards a common RT-level subset of VHDL

    Publication Year: 1992
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (61 KB)

    Summary form only given. The activities and goals of the European working group on synthesis requirements for VHSIC hardware description language (VHDL) are described. Some of the problems concerning the use of VHDL at RT level are reported. A formal model for hardware semantics of RT-level VHDL could rely on deterministic automata. This is important for the cooperation of synthesis and formal ver... View full abstract»

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  • EURO-DAC '92. European Design Automation Conference, EURO-VHDL '92 (Cat. No.92CH3126-0)

    Publication Year: 1992
    Request permission for commercial reuse | PDF file iconPDF (20 KB)
    Freely Available from IEEE
  • Challenges for CAD in computer development in the 1990s

    Publication Year: 1992, Page(s):597 - 598
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (98 KB)

    Summary form only given. CAD tools play a key role in determining the productivity and the time-to-market of computer development. To predict future trends in CAD, the future trends of technology and computer architecture have to be considered because of its strong interaction with tools and design methodology. The current computer development methodology is summarized. The CAD tools supporting th... View full abstract»

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  • A fast and accurate characterization method for full-CMOS circuits

    Publication Year: 1992, Page(s):410 - 415
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current ... View full abstract»

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  • An exact analytic technique for simulating uniform RC lines

    Publication Year: 1992, Page(s):416 - 420
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    A new technique, based on convolution, has been developed for the time domain simulation of uniform RC lines. This technique is exact, requiring no simplification of the line's internal mechanism. It is shown that though the impulse responses of uniform RC lines are ill-behaved and unsuitable for direct numerical implementation, the use of a convolutional formula obtained by generalizing the trape... View full abstract»

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  • A dynamic scheduling algorithm for the simulation of MOS and bipolar circuits using waveform relaxation

    Publication Year: 1992, Page(s):421 - 426
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    A new scheduling algorithm for waveform relaxation is presented. The algorithm is based on information about the circuit structure and the dynamic behavior of the circuit. As the new scheduling algorithm does not depend on the circuit technology, bipolar circuits can also be simulated using the waveform relaxation method. The examples presented show a speedup factor of two compared to other schedu... View full abstract»

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  • Interest of a VHDL native environment

    Publication Year: 1992, Page(s):684 - 685
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    A VHSIC hardware description language (VHDL) native environment enables the use of VHDL in the design of accurate tools. The author reports on the Perennity constraint, portability, coding strategy, and possible improvements. A VHDL native environment example is provided View full abstract»

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  • SPADES: a simulator for path delay faults in sequential circuits

    Publication Year: 1992, Page(s):428 - 435
    Cited by:  Papers (28)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    A fault simulator for path delay faults in synchronous sequential circuits is described, where a test sequence is considered under different combinations of slow and fast clock cycles (clocking schemes). The features of the simulator are: (1) multiple clocking schemes used for the application of a given test sequence are considered in parallel, allowing fast fault simulation for a given sequence, ... View full abstract»

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  • Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up

    Publication Year: 1992, Page(s):436 - 441
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Several methods accelerating fault simulation for combinational circuits using parallel pattern evaluation are presented. All methods make use of a very efficient data structure which allows the easy recognition of special situations that can be used to avoid a lot of gate evaluations during explicit fault simulation. An implementation of the concepts shows that the resulting fault simulation algo... View full abstract»

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  • VHDL intermediate format standardization activity: status and trends

    Publication Year: 1992, Page(s):687 - 688
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    The VIFASG is a Design Automation Standards Subcommittee (DASS) subgroup which was setup to develop a proposal for a standard intermediate format representation of VHSIC hardware description language (VHDL) models. The status of the current proposal and the remaining issues to be addressed are summarized View full abstract»

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  • Linear time fault simulation algorithm using a content addressable memory

    Publication Year: 1992, Page(s):442 - 445
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type pa... View full abstract»

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  • Temporal verification of behavioral descriptions in VHDL

    Publication Year: 1992, Page(s):692 - 697
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    An approach for verifying the temporal scheduling of behavioral models of VHSIC hardware description language (VHDL) is presented. The aim is to verify that the control flow of a behavioral description satisfies its behavioral specifications described in a formalism based on reified temporal logics, and on a notion of physical activity. From this formalism, a verification procedure is established ... View full abstract»

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  • SEESIM-a fast synchronous sequential circuit fault simulator with single event equivalence

    Publication Year: 1992, Page(s):446 - 449
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The authors present a sequential circuit fault simulator of `single event equivalent', which combines the advantages of several techniques: fanout-free region, critical path tracing, and the dominator, techniques which were previously only applicable to combinational fault simulation. The simulator requires the minimal amount of memory, and its speed is superior to that of a state-of-the-art concu... View full abstract»

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  • Providing a VHDL-interface for proof systems

    Publication Year: 1992, Page(s):698 - 703
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    When integrating formal methods into the design process, VHSIC hardware description language (VHDL) is unavoidable. A VHDL front end for the proof system LAMBDA is presented. The idea is to provide support for almost the full VHDL language and to generate executable ML descriptions that closely resemble the original VHDL programs. Choosing a purely functional approach has the benefit that the gene... View full abstract»

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  • On modeling integrated design environments

    Publication Year: 1992, Page(s):452 - 458
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The authors describe an approach towards modeling the heterogeneous aspects of design environments which is based on a paradigm of separation and integration, yielding an adequate, well structured, non-redundant, and integrated design model for generic design environments. The design model consists of five partial models: (1) design flow model; (2) design tool model; (3) design structure model; (4... View full abstract»

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  • Towards a standard VHDL synthesis package

    Publication Year: 1992, Page(s):706 - 712
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    The VHSIC hardware description language (VHDL) Synthesis Special Interest Group (SSIG) has been working on the development of a standard VHDL package for synthesis. The efforts of the group have been divided into four different areas: logic type, representation of numeric types, specification of constraints, and special identifications. Each of these areas addresses an important part of the inform... View full abstract»

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  • Information modelling of folded and unfolded design

    Publication Year: 1992, Page(s):459 - 464
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    An information model for a folded design description which corresponds to electronic design interchange format (EDIF) version 2.0.0, using the language Express, is presented. It is shown that it can be easily extended to a model for an unfolded description. A method to compute the actual values for occurrences of views, nets, and ports, is given, which is based on the back-annotation facilities of... View full abstract»

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  • ALU synthesis from HDL descriptions to optimized multi-level logic

    Publication Year: 1992, Page(s):175 - 180
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The author presents a new tool for automatic ALU (arithmetic and logic unit) synthesis that combines the translation from an HDL to logic level and subsequent multi-level logic synthesis. The existing tools treat ALUs as random logic in that they neglect the regularity of ALUs. These tools do not achieve good results for ALUs. In contrast, the described tool partitions the ALU into blocks such as ... View full abstract»

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  • VHDL analog extensions: process, issues, and status

    Publication Year: 1992, Page(s):713 - 717
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The activity involved in developing language extensions to VHSIC hardware description languages (VHDL) to provide a mixed-mode digital/analog descriptive capability is presented. The history of the organization that is responsible for developing these extensions is presented. The process being used to develop the standard is described, along with a progress report. The general guidelines being fol... View full abstract»

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  • Chip assembly in the PLAYOUT VLSI design system

    Publication Year: 1992, Page(s):215 - 221
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    Chip assembly in PLAYOUT is designed for top-down chip planning. An example of a three-level hierarchy demonstrates the new design strategy. Three-phase chip planning and chip assembly have close interaction to guarantee an exchange of constraints between levels of the hierarchy. Chip assembly is composed of two different functions: cell synthesis, and cell assembly. For cell synthesis, standard c... View full abstract»

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  • Locating logic design errors via test generation and don't-care propagation

    Publication Year: 1992, Page(s):466 - 471
    Cited by:  Papers (27)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The author presents a new technique, the don't-care propagation method, for logic verification and design error location in a circuit. Test patterns for single stuck-line faults are used to compare the gate-level implementation of a circuit with its functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree wit... View full abstract»

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  • VHDL for high speed desktop video ICs-experience with replacement of other simulator

    Publication Year: 1992, Page(s):652 - 657
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    A simulation methodology used for high-speed digital video processing IC development is described. The simulation environment is optimized to meet application-specific requirements for the efficient hierarchical mixed-level simulation of large stimuli sets. To increase design efficiency, the simulation flow has been adapted to VHSIC hardware description language (VHDL). Details of the implementati... View full abstract»

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  • Performance-driven interconnection optimization for microarchitecture synthesis

    Publication Year: 1992, Page(s):118 - 123
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    The interconnection synthesis problem in microarchitecture-level designs is addressed. With emphasis on the speed of data movement operations, algorithms are proposed that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. Two types of problems are considered: resource-constrained binding and performance-constrained binding. The integer linear ... View full abstract»

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